1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s 2 3fminv b0, p7, z31.b 4// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 5// CHECK-NEXT: fminv b0, p7, z31.b 6// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 7 8 9// ------------------------------------------------------------------------- // 10// Invalid predicate operand 11 12 13fminv h0, p8, z31.h 14// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) 15// CHECK-NEXT: fminv h0, p8, z31.h 16// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 17 18fminv h0, p7.b, z31.h 19// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) 20// CHECK-NEXT: fminv h0, p7.b, z31.h 21// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 22 23fminv h0, p7.q, z31.h 24// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) 25// CHECK-NEXT: fminv h0, p7.q, z31.h 26// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 27 28 29// ------------------------------------------------------------------------- // 30// Result must be a valid FP register. 31 32fminv v0, p7, z31.h 33// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 34// CHECK-NEXT: fminv v0, p7, z31.h 35// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 36 37// --------------------------------------------------------------------------// 38// Negative tests for instructions that are incompatible with movprfx 39 40movprfx z31.d, p7/z, z6.d 41fminv d0, p7, z31.d 42// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 43// CHECK-NEXT: fminv d0, p7, z31.d 44// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 45 46movprfx z31, z6 47fminv d0, p7, z31.d 48// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 49// CHECK-NEXT: fminv d0, p7, z31.d 50// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 51