xref: /llvm-project/llvm/test/MC/AArch64/SME2p1/fcvtl-diagnostics.s (revision 1b2f970e9f40eb2a3bd082b6a660d4f58ba4f59b) 
1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 2>&1 < %s | FileCheck %s
2
3// --------------------------------------------------------------------------//
4// Invalid vector list
5
6fcvtl {z0.s-z2.s}, z0.h
7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8// CHECK-NEXT: fcvtl {z0.s-z2.s}, z0.h
9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10
11fcvtl z0.h, {z1.s-z2.s}
12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
13// CHECK-NEXT:  fcvtl z0.h, {z1.s-z2.s}
14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15
16fcvtl {z1.s-z2.s}, z0.h
17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
18// CHECK-NEXT:  fcvtl {z1.s-z2.s}, z0.h
19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20
21// --------------------------------------------------------------------------//
22// Invalid Register Suffix
23
24fcvtl {z0.s-z1.s}, z0.s
25// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
26// CHECK-NEXT: fcvtl {z0.s-z1.s}, z0.s
27// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
28
29fcvtl {z0.h-z1.h}, z0.h
30// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
31// CHECK-NEXT: fcvtl {z0.h-z1.h}, z0.h
32// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
33