1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s 2 3// --------------------------------------------------------------------------// 4// Invalid vector list 5 6fcvt z0.h, {z0.s-z2.s} 7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 8// CHECK-NEXT: fcvt z0.h, {z0.s-z2.s} 9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 10 11fcvt {z0.s-z2.s}, z0.h 12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 13// CHECK-NEXT: fcvt {z0.s-z2.s}, z0.h 14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 15 16fcvt z0.h, {z1.s-z2.s} 17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types 18// CHECK-NEXT: fcvt z0.h, {z1.s-z2.s} 19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 20 21fcvt {z1.s-z2.s}, z0.h 22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types 23// CHECK-NEXT: fcvt {z1.s-z2.s}, z0.h 24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 25 26// --------------------------------------------------------------------------// 27// Invalid Register Suffix 28 29fcvt z0.s, {z0.s-z1.s} 30// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 31// CHECK-NEXT: fcvt z0.s, {z0.s-z1.s} 32// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 33 34fcvt z0.h, {z0.h-z1.h} 35// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 36// CHECK-NEXT: fcvt z0.h, {z0.h-z1.h} 37// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 38 39fcvt {z0.s-z1.s}, z0.s 40// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 41// CHECK-NEXT: fcvt {z0.s-z1.s}, z0.s 42// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 43 44fcvt {z0.h-z1.h}, z0.h 45// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 46// CHECK-NEXT: fcvt {z0.h-z1.h}, z0.h 47// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 48