1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s 2 3// --------------------------------------------------------------------------// 4// Invalid vector list 5 6fmaxnm {z0.d, z1.d}, {z0.d-z2.d}, z0.d 7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 8// CHECK-NEXT: fmaxnm {z0.d, z1.d}, {z0.d-z2.d}, z0.d 9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 10 11fmaxnm {z1.s-z2.s}, {z0.s, z1.s}, z0.s 12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type 13// CHECK-NEXT: fmaxnm {z1.s-z2.s}, {z0.s, z1.s}, z0.s 14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 15 16// --------------------------------------------------------------------------// 17// Invalid single register 18 19fmaxnm {z0.h, z1.h}, {z2.h-z3.h}, z31.h 20// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h 21// CHECK-NEXT: fmaxnm {z0.h, z1.h}, {z2.h-z3.h}, z31.h 22// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 23 24// --------------------------------------------------------------------------// 25// Invalid Register Suffix 26 27fmaxnm {z0.h, z1.h}, {z2.h-z3.h}, z14.d 28// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h 29// CHECK-NEXT: fmaxnm {z0.h, z1.h}, {z2.h-z3.h}, z14.d 30// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 31