xref: /llvm-project/llvm/test/MC/AArch64/SME2/fcvtzu-diagnostics.s (revision 440005b3c3531901563b0a16834e013ecb973f66) 
1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
2
3// --------------------------------------------------------------------------//
4// Invalid vector list
5
6fcvtzu {z0.s-z1.s}, {z0.s-z2.s}
7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8// CHECK-NEXT: fcvtzu {z0.s-z1.s}, {z0.s-z2.s}
9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10
11fcvtzu {z1.s-z2.s}, {z0.s-z1.s}
12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
13// CHECK-NEXT:  fcvtzu {z1.s-z2.s}, {z0.s-z1.s}
14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15
16// --------------------------------------------------------------------------//
17// Invalid Register Suffix
18
19fcvtzu {z0.d-z1.d}, {z0.s-z1.s}
20// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
21// CHECK-NEXT: fcvtzu {z0.d-z1.d}, {z0.s-z1.s}
22// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23
24