1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+fp8 2>&1 < %s| FileCheck %s 2 3// --------------------------------------------------------------------------// 4// Incorrect operand 5 6f1cvt { z0.h, z1.h }, z0 7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression 8// CHECK-NEXT: f1cvt { z0.h, z1.h }, z0 9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 10 11bf1cvt { z0, z1 }, z0.b 12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 13// CHECK-NEXT: bf1cvt { z0, z1 }, z0.b 14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 15 16bf1cvtl { z0.b, z1.b }, z0.b 17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 18// CHECK-NEXT: bf1cvtl { z0.b, z1.b }, z0.b 19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 20 21bf2cvt { z0.h, z1.h }, z0.h 22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 23// CHECK-NEXT: bf2cvt { z0.h, z1.h }, z0.h 24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 25 26bf2cvtl { z30.h}, z31.b 27// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 28// CHECK-NEXT: bf2cvtl { z30.h}, z31.b 29// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 30 31f2cvt { z0, z1.h }, {z0.b} 32// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix 33// CHECK-NEXT: f2cvt { z0, z1.h }, {z0.b} 34// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 35 36f2cvtl z0.h, z1.h, z0.b 37// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 38// CHECK-NEXT: f2cvtl z0.h, z1.h, z0.b 39// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 40 41fcvt z31.b, { z30.h } 42// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 43// CHECK-NEXT: fcvt z31.b, { z30.h } 44// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 45 46bfcvt z0.b, { z0.b, z1.b } 47// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 48// CHECK-NEXT: bfcvt z0.b, { z0.b, z1.b } 49// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 50 51// --------------------------------------------------------------------------// 52// Incorrect range of vectors 53 54bf1cvt { z1.h, z2.h }, z0.b 55// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types 56// CHECK-NEXT: bf1cvt { z1.h, z2.h }, z0.b 57// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 58 59f1cvt { z1.h, z0.h }, z31.b 60// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 61// CHECK-NEXT: f1cvt { z1.h, z0.h }, z31.b 62// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 63 64f1cvtl { z31.h, z0.h }, z0.b 65// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types 66// CHECK-NEXT: f1cvtl { z31.h, z0.h }, z0.b 67// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 68 69fcvt z31.b, { z29.s - z0.s } 70// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types 71// CHECK-NEXT: fcvt z31.b, { z29.s - z0.s } 72// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 73 74fcvtn z31.b, { z30.s - z1.s } 75// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types 76// CHECK-NEXT: fcvtn z31.b, { z30.s - z1.s } 77// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 78 79fcvtn z0.b, { z31.s - z2.s } 80// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types 81// CHECK-NEXT: fcvtn z0.b, { z31.s - z2.s } 82// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 83 84fcvtn z0.b, { z1.s - z4.s } 85// CHECK: [[@LINE-1]]:{{[0-9]+}}: 86// CHECK-NEXT: fcvtn z0.b, { z1.s - z4.s } 87// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 88