1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 2; Test that alloca instrumentation with old API levels does not use short granules. 3; 4; RUN: opt < %s -passes=hwasan -S | FileCheck %s 5 6target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" 7target triple = "aarch64--linux-android" 8 9declare void @use32(ptr) 10 11define void @test_alloca() sanitize_hwaddress { 12; CHECK-LABEL: define void @test_alloca 13; CHECK-SAME: () #[[ATTR0:[0-9]+]] { 14; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() 15; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 16; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 17; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 18; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) 19; CHECK-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) 20; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 21; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 22; CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] 23; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr 24; CHECK-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 8 25; CHECK-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 26; CHECK-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 27; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 28; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 29; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] 30; CHECK-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 8 31; CHECK-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 32; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 33; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr 34; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 35; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 36; CHECK-NEXT: [[TMP18:%.*]] = xor i64 [[TMP4]], 0 37; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[X]] to i64 38; CHECK-NEXT: [[TMP20:%.*]] = and i64 [[TMP19]], 72057594037927935 39; CHECK-NEXT: [[TMP21:%.*]] = shl i64 [[TMP18]], 56 40; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP20]], [[TMP21]] 41; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP22]] to ptr 42; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[TMP18]] to i8 43; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[X]] to i64 44; CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 72057594037927935 45; CHECK-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 46; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] 47; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP27]], i8 [[TMP23]], i64 1, i1 false) 48; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]) 49; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 50; CHECK-NEXT: [[TMP29:%.*]] = ptrtoint ptr [[X]] to i64 51; CHECK-NEXT: [[TMP30:%.*]] = and i64 [[TMP29]], 72057594037927935 52; CHECK-NEXT: [[TMP31:%.*]] = lshr i64 [[TMP30]], 4 53; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP31]] 54; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP32]], i8 [[TMP28]], i64 1, i1 false) 55; CHECK-NEXT: ret void 56; 57 %x = alloca i32, align 4 58 call void @use32(ptr nonnull %x) 59 ret void 60} 61