1; RUN: opt < %s -passes=dfsan -dfsan-track-origins=1 -S | FileCheck %s 2; 3; %i13 and %i15 have the same key in shadow cache. They should not reuse the same 4; shadow because their blocks do not dominate each other. Origin tracking 5; splt blocks. This test ensures DT is updated correctly, and cached shadows 6; are not mis-used. 7target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" 8target triple = "x86_64-unknown-linux-gnu" 9 10; CHECK: @__dfsan_arg_tls = external thread_local(initialexec) global [[TLS_ARR:\[100 x i64\]]] 11define void @cached_shadows(double %arg) { 12 ; CHECK: @cached_shadows.dfsan 13 ; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 14 ; CHECK: [[AS:%.*]] = load i8, ptr @__dfsan_arg_tls, align [[ALIGN:2]] 15 ; CHECK: [[L1:.+]]: 16 ; CHECK: {{.*}} = phi i8 17 ; CHECK: {{.*}} = phi i32 18 ; CHECK: {{.*}} = phi double [ 3.000000e+00 19 ; CHECK: [[S_L1:%.*]] = phi i8 [ 0, %[[L0:.*]] ], [ [[S_L7:%.*]], %[[L7:.*]] ] 20 ; CHECK: [[O_L1:%.*]] = phi i32 [ 0, %[[L0]] ], [ [[O_L7:%.*]], %[[L7]] ] 21 ; CHECK: [[V_L1:%.*]] = phi double [ 4.000000e+00, %[[L0]] ], [ [[V_L7:%.*]], %[[L7]] ] 22 ; CHECK: br i1 {{%.+}}, label %[[L2:.*]], label %[[L4:.*]] 23 ; CHECK: [[L2]]: 24 ; CHECK: br i1 {{%.+}}, label %[[L3:.+]], label %[[L7]] 25 ; CHECK: [[L3]]: 26 ; CHECK: [[S_L3:%.*]] = or i8 27 ; CHECK: [[AS_NE_L3:%.*]] = icmp ne i8 [[AS]], 0 28 ; CHECK: [[O_L3:%.*]] = select i1 [[AS_NE_L3]], i32 %{{[0-9]+}}, i32 [[O_L1]] 29 ; CHECK: [[V_L3:%.*]] = fsub double [[V_L1]], %{{.+}} 30 ; CHECK: br label %[[L7]] 31 ; CHECK: [[L4]]: 32 ; CHECK: br i1 %_dfscmp, label %[[L5:.+]], label %[[L6:.+]], 33 ; CHECK: [[L5]]: 34 ; CHECK: br label %[[L6]] 35 ; CHECK: [[L6]]: 36 ; CHECK: [[S_L6:%.*]] = or i8 37 ; CHECK: [[AS_NE_L6:%.*]] = icmp ne i8 [[AS]], 0 38 ; CHECK: [[O_L6:%.*]] = select i1 [[AS_NE_L6]], i32 [[AO]], i32 [[O_L1]] 39 ; CHECK: [[V_L6:%.*]] = fadd double [[V_L1]], %{{.+}} 40 ; CHECK: br label %[[L7]] 41 ; CHECK: [[L7]]: 42 ; CHECK: [[S_L7]] = phi i8 [ [[S_L3]], %[[L3]] ], [ [[S_L1]], %[[L2]] ], [ [[S_L6]], %[[L6]] ] 43 ; CHECK: [[O_L7]] = phi i32 [ [[O_L3]], %[[L3]] ], [ [[O_L1]], %[[L2]] ], [ [[O_L6]], %[[L6]] ] 44 ; CHECK: [[V_L7]] = phi double [ [[V_L3]], %[[L3]] ], [ [[V_L1]], %[[L2]] ], [ [[V_L6]], %[[L6]] ] 45 ; CHECK: br i1 %{{.+}}, label %[[L1]], label %[[L8:.+]] 46 ; CHECK: [[L8]]: 47bb: 48 %i = alloca double, align 8 49 %i1 = alloca double, align 8 50 %i2 = bitcast ptr %i to ptr 51 store volatile double 1.000000e+00, ptr %i, align 8 52 %i3 = bitcast ptr %i1 to ptr 53 store volatile double 2.000000e+00, ptr %i1, align 8 54 br label %bb4 55 56bb4: ; preds = %bb16, %bb 57 %i5 = phi double [ 3.000000e+00, %bb ], [ %i17, %bb16 ] 58 %i6 = phi double [ 4.000000e+00, %bb ], [ %i18, %bb16 ] 59 %i7 = load volatile double, ptr %i1, align 8 60 %i8 = fcmp une double %i7, 0.000000e+00 61 %i9 = load volatile double, ptr %i1, align 8 62 br i1 %i8, label %bb10, label %bb14 63 64bb10: ; preds = %bb4 65 %i11 = fcmp une double %i9, 0.000000e+00 66 br i1 %i11, label %bb12, label %bb16 67 68bb12: ; preds = %bb10 69 %i13 = fsub double %i6, %arg 70 br label %bb16 71 72bb14: ; preds = %bb4 73 store volatile double %i9, ptr %i, align 8 74 %i15 = fadd double %i6, %arg 75 br label %bb16 76 77bb16: ; preds = %bb14, %bb12, %bb10 78 %i17 = phi double [ %i6, %bb12 ], [ %i5, %bb10 ], [ %i6, %bb14 ] 79 %i18 = phi double [ %i13, %bb12 ], [ %i6, %bb10 ], [ %i15, %bb14 ] 80 %i19 = fcmp olt double %i17, 9.900000e+01 81 br i1 %i19, label %bb4, label %bb20 82 83bb20: ; preds = %bb16 84 ret void 85} 86