xref: /llvm-project/llvm/test/Instrumentation/AddressSanitizer/X86/asm_cpuid.ll (revision 855fe35064674c4601ea9c659a015cacdcec9f63)
1; RUN: opt < %s -passes=asan -S -o %t.ll
2; RUN: FileCheck %s < %t.ll
3; RUN: llc < %t.ll | FileCheck %s --check-prefix=ASM
4
5target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-S32"
6target triple = "i386-pc-windows-msvc"
7
8define void @MyCPUID(i32 %fxn, ptr %out) sanitize_address {
9  %fxn.ptr = alloca i32
10  %a.ptr = alloca i32
11  %b.ptr = alloca i32
12  %c.ptr = alloca i32
13  %d.ptr = alloca i32
14  store i32 %fxn, ptr %fxn.ptr
15  call void asm sideeffect inteldialect "xchg ebx, esi\0A\09mov eax, dword ptr $4\0A\09cpuid\0A\09mov dword ptr $0, eax\0A\09mov dword ptr $1, ebx\0A\09mov dword ptr $2, ecx\0A\09mov dword ptr $3, edx\0A\09xchg ebx, esi", "=*m,=*m,=*m,=*m,*m,~{eax},~{ebx},~{ecx},~{edx},~{esi},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) %a.ptr, ptr elementtype(i32) %b.ptr, ptr elementtype(i32) %c.ptr, ptr elementtype(i32) %d.ptr, ptr elementtype(i32) %fxn.ptr)
16
17  %a = load i32, ptr %a.ptr
18  store i32 %a, ptr %out
19
20  %b = load i32, ptr %b.ptr
21  %b.out = getelementptr inbounds i32, ptr %out, i32 1
22  store i32 %b, ptr %b.out
23
24  %c = load i32, ptr %c.ptr
25  %c.out = getelementptr inbounds i32, ptr %out, i32 2
26  store i32 %c, ptr %c.out
27
28  %d = load i32, ptr %d.ptr
29  %d.out = getelementptr inbounds i32, ptr %out, i32 3
30  store i32 %d, ptr %d.out
31
32  ret void
33}
34
35; We used to introduce stack mallocs for UAR detection, but that makes LLVM run
36; out of registers on 32-bit platforms. Therefore, we don't do stack malloc on
37; such functions.
38
39; CHECK-LABEL: define void @MyCPUID(i32 %fxn, ptr %out)
40; CHECK: %MyAlloca = alloca [96 x i8], align 32
41; CHECK-NOT: call {{.*}} @__asan_stack_malloc
42
43; The code generator should recognize that all operands are just stack memory.
44; This is important with MS inline asm where operand lists are implicit and all
45; local variables can be referenced freely.
46
47; ASM-LABEL: MyCPUID:
48; ASM:      cpuid
49; ASM-NEXT: movl    %eax, {{[0-9]+}}(%esp)
50; ASM-NEXT: movl    %ebx, {{[0-9]+}}(%esp)
51; ASM-NEXT: movl    %ecx, {{[0-9]+}}(%esp)
52; ASM-NEXT: movl    %edx, {{[0-9]+}}(%esp)
53