1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 2; RUN: opt < %s -passes=asan -S | FileCheck %s 3; RUN: opt < %s -passes=asan -asan-recover -S | FileCheck %s --check-prefix=RECOV 4target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" 5target triple = "amdgcn-amd-amdhsa" 6 7define protected amdgpu_kernel void @global_store(ptr addrspace(1) %p, i32 %i) sanitize_address { 8; CHECK-LABEL: define protected amdgpu_kernel void @global_store( 9; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] { 10; CHECK-NEXT: entry: 11; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64 12; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 13; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 14; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr 15; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 16; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 17; CHECK-NEXT: [[TMP6:%.*]] = and i64 [[TMP0]], 7 18; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 3 19; CHECK-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i8 20; CHECK-NEXT: [[TMP9:%.*]] = icmp sge i8 [[TMP8]], [[TMP4]] 21; CHECK-NEXT: [[TMP10:%.*]] = and i1 [[TMP5]], [[TMP9]] 22; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP10]]) 23; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i64 [[TMP11]], 0 24; CHECK-NEXT: br i1 [[TMP12]], label [[ASAN_REPORT:%.*]], label [[TMP15:%.*]], !prof [[PROF0:![0-9]+]] 25; CHECK: asan.report: 26; CHECK-NEXT: br i1 [[TMP10]], label [[TMP13:%.*]], label [[TMP14:%.*]] 27; CHECK: 13: 28; CHECK-NEXT: call void @__asan_report_store4(i64 [[TMP0]]) #[[ATTR5:[0-9]+]] 29; CHECK-NEXT: call void @llvm.amdgcn.unreachable() 30; CHECK-NEXT: br label [[TMP14]] 31; CHECK: 14: 32; CHECK-NEXT: br label [[TMP15]] 33; CHECK: 15: 34; CHECK-NEXT: store i32 0, ptr addrspace(1) [[P]], align 4 35; CHECK-NEXT: ret void 36; 37; RECOV-LABEL: define protected amdgpu_kernel void @global_store( 38; RECOV-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] { 39; RECOV-NEXT: entry: 40; RECOV-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64 41; RECOV-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 42; RECOV-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 43; RECOV-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr 44; RECOV-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 45; RECOV-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 46; RECOV-NEXT: [[TMP6:%.*]] = and i64 [[TMP0]], 7 47; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 3 48; RECOV-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i8 49; RECOV-NEXT: [[TMP9:%.*]] = icmp sge i8 [[TMP8]], [[TMP4]] 50; RECOV-NEXT: [[TMP10:%.*]] = and i1 [[TMP5]], [[TMP9]] 51; RECOV-NEXT: br i1 [[TMP10]], label [[ASAN_REPORT:%.*]], label [[TMP11:%.*]], !prof [[PROF0:![0-9]+]] 52; RECOV: asan.report: 53; RECOV-NEXT: call void @__asan_report_store4_noabort(i64 [[TMP0]]) #[[ATTR3:[0-9]+]] 54; RECOV-NEXT: br label [[TMP11]] 55; RECOV: 11: 56; RECOV-NEXT: store i32 0, ptr addrspace(1) [[P]], align 4 57; RECOV-NEXT: ret void 58; 59entry: 60 61 store i32 0, ptr addrspace(1) %p, align 4 62 ret void 63} 64 65define protected amdgpu_kernel void @global_load(ptr addrspace(1) %p, i32 %i) sanitize_address { 66; CHECK-LABEL: define protected amdgpu_kernel void @global_load( 67; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0]] { 68; CHECK-NEXT: entry: 69; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64 70; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 71; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 72; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr 73; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 74; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 75; CHECK-NEXT: [[TMP6:%.*]] = and i64 [[TMP0]], 7 76; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 3 77; CHECK-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i8 78; CHECK-NEXT: [[TMP9:%.*]] = icmp sge i8 [[TMP8]], [[TMP4]] 79; CHECK-NEXT: [[TMP10:%.*]] = and i1 [[TMP5]], [[TMP9]] 80; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP10]]) 81; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i64 [[TMP11]], 0 82; CHECK-NEXT: br i1 [[TMP12]], label [[ASAN_REPORT:%.*]], label [[TMP15:%.*]], !prof [[PROF0]] 83; CHECK: asan.report: 84; CHECK-NEXT: br i1 [[TMP10]], label [[TMP13:%.*]], label [[TMP14:%.*]] 85; CHECK: 13: 86; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP0]]) #[[ATTR5]] 87; CHECK-NEXT: call void @llvm.amdgcn.unreachable() 88; CHECK-NEXT: br label [[TMP14]] 89; CHECK: 14: 90; CHECK-NEXT: br label [[TMP15]] 91; CHECK: 15: 92; CHECK-NEXT: [[Q:%.*]] = load i32, ptr addrspace(1) [[P]], align 4 93; CHECK-NEXT: ret void 94; 95; RECOV-LABEL: define protected amdgpu_kernel void @global_load( 96; RECOV-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0]] { 97; RECOV-NEXT: entry: 98; RECOV-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64 99; RECOV-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 100; RECOV-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 101; RECOV-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr 102; RECOV-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 103; RECOV-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 104; RECOV-NEXT: [[TMP6:%.*]] = and i64 [[TMP0]], 7 105; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 3 106; RECOV-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i8 107; RECOV-NEXT: [[TMP9:%.*]] = icmp sge i8 [[TMP8]], [[TMP4]] 108; RECOV-NEXT: [[TMP10:%.*]] = and i1 [[TMP5]], [[TMP9]] 109; RECOV-NEXT: br i1 [[TMP10]], label [[ASAN_REPORT:%.*]], label [[TMP11:%.*]], !prof [[PROF0]] 110; RECOV: asan.report: 111; RECOV-NEXT: call void @__asan_report_load4_noabort(i64 [[TMP0]]) #[[ATTR3]] 112; RECOV-NEXT: br label [[TMP11]] 113; RECOV: 11: 114; RECOV-NEXT: [[Q:%.*]] = load i32, ptr addrspace(1) [[P]], align 4 115; RECOV-NEXT: ret void 116; 117entry: 118 119 %q = load i32, ptr addrspace(1) %p, align 4 120 ret void 121} 122 123define protected amdgpu_kernel void @global_store_8(ptr addrspace(1) %p) sanitize_address { 124; CHECK-LABEL: define protected amdgpu_kernel void @global_store_8( 125; CHECK-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] { 126; CHECK-NEXT: entry: 127; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64 128; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 129; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 130; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr 131; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 132; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 133; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP5]]) 134; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP6]], 0 135; CHECK-NEXT: br i1 [[TMP7]], label [[ASAN_REPORT:%.*]], label [[TMP10:%.*]], !prof [[PROF0]] 136; CHECK: asan.report: 137; CHECK-NEXT: br i1 [[TMP5]], label [[TMP8:%.*]], label [[TMP9:%.*]] 138; CHECK: 8: 139; CHECK-NEXT: call void @__asan_report_store8(i64 [[TMP0]]) #[[ATTR5]] 140; CHECK-NEXT: call void @llvm.amdgcn.unreachable() 141; CHECK-NEXT: br label [[TMP9]] 142; CHECK: 9: 143; CHECK-NEXT: br label [[TMP10]] 144; CHECK: 10: 145; CHECK-NEXT: store i64 0, ptr addrspace(1) [[P]], align 8 146; CHECK-NEXT: ret void 147; 148; RECOV-LABEL: define protected amdgpu_kernel void @global_store_8( 149; RECOV-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] { 150; RECOV-NEXT: entry: 151; RECOV-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64 152; RECOV-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 153; RECOV-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 154; RECOV-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr 155; RECOV-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 156; RECOV-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 157; RECOV-NEXT: br i1 [[TMP5]], label [[ASAN_REPORT:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] 158; RECOV: asan.report: 159; RECOV-NEXT: call void @__asan_report_store8_noabort(i64 [[TMP0]]) #[[ATTR3]] 160; RECOV-NEXT: br label [[TMP6]] 161; RECOV: 6: 162; RECOV-NEXT: store i64 0, ptr addrspace(1) [[P]], align 8 163; RECOV-NEXT: ret void 164; 165entry: 166 store i64 0, ptr addrspace(1) %p, align 8 167 ret void 168} 169 170define protected amdgpu_kernel void @global_load_8(ptr addrspace(1) %p) sanitize_address { 171; CHECK-LABEL: define protected amdgpu_kernel void @global_load_8( 172; CHECK-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] { 173; CHECK-NEXT: entry: 174; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64 175; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 176; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 177; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr 178; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 179; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 180; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP5]]) 181; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP6]], 0 182; CHECK-NEXT: br i1 [[TMP7]], label [[ASAN_REPORT:%.*]], label [[TMP10:%.*]], !prof [[PROF0]] 183; CHECK: asan.report: 184; CHECK-NEXT: br i1 [[TMP5]], label [[TMP8:%.*]], label [[TMP9:%.*]] 185; CHECK: 8: 186; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP0]]) #[[ATTR5]] 187; CHECK-NEXT: call void @llvm.amdgcn.unreachable() 188; CHECK-NEXT: br label [[TMP9]] 189; CHECK: 9: 190; CHECK-NEXT: br label [[TMP10]] 191; CHECK: 10: 192; CHECK-NEXT: [[Q:%.*]] = load i64, ptr addrspace(1) [[P]], align 8 193; CHECK-NEXT: ret void 194; 195; RECOV-LABEL: define protected amdgpu_kernel void @global_load_8( 196; RECOV-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] { 197; RECOV-NEXT: entry: 198; RECOV-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64 199; RECOV-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 200; RECOV-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 201; RECOV-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr 202; RECOV-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 203; RECOV-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 204; RECOV-NEXT: br i1 [[TMP5]], label [[ASAN_REPORT:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] 205; RECOV: asan.report: 206; RECOV-NEXT: call void @__asan_report_load8_noabort(i64 [[TMP0]]) #[[ATTR3]] 207; RECOV-NEXT: br label [[TMP6]] 208; RECOV: 6: 209; RECOV-NEXT: [[Q:%.*]] = load i64, ptr addrspace(1) [[P]], align 8 210; RECOV-NEXT: ret void 211; 212entry: 213 %q = load i64, ptr addrspace(1) %p, align 8 214 ret void 215} 216