1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 2; RUN: opt < %s -passes=asan -S | FileCheck %s 3; RUN: opt < %s -passes=asan -asan-recover -S | FileCheck %s --check-prefix=RECOV 4target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" 5target triple = "amdgcn-amd-amdhsa" 6 7@x = addrspace(4) global [2 x i32] zeroinitializer, align 4 8@x8 = addrspace(4) global [2 x i64] zeroinitializer, align 8 9 10define protected amdgpu_kernel void @constant_load(i64 %i) sanitize_address { 11; CHECK-LABEL: define protected amdgpu_kernel void @constant_load( 12; CHECK-SAME: i64 [[I:%.*]]) #[[ATTR0:[0-9]+]] { 13; CHECK-NEXT: entry: 14; CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(4) @x, i64 0, i64 [[I]] 15; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(4) [[A]] to i64 16; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 17; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 18; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr 19; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 20; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 21; CHECK-NEXT: [[TMP6:%.*]] = and i64 [[TMP0]], 7 22; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 3 23; CHECK-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i8 24; CHECK-NEXT: [[TMP9:%.*]] = icmp sge i8 [[TMP8]], [[TMP4]] 25; CHECK-NEXT: [[TMP10:%.*]] = and i1 [[TMP5]], [[TMP9]] 26; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP10]]) 27; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i64 [[TMP11]], 0 28; CHECK-NEXT: br i1 [[TMP12]], label [[ASAN_REPORT:%.*]], label [[TMP15:%.*]], !prof [[PROF2:![0-9]+]] 29; CHECK: asan.report: 30; CHECK-NEXT: br i1 [[TMP10]], label [[TMP13:%.*]], label [[TMP14:%.*]] 31; CHECK: 13: 32; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP0]]) #[[ATTR5:[0-9]+]] 33; CHECK-NEXT: call void @llvm.amdgcn.unreachable() 34; CHECK-NEXT: br label [[TMP14]] 35; CHECK: 14: 36; CHECK-NEXT: br label [[TMP15]] 37; CHECK: 15: 38; CHECK-NEXT: [[Q:%.*]] = load i32, ptr addrspace(4) [[A]], align 4 39; CHECK-NEXT: ret void 40; 41; RECOV-LABEL: define protected amdgpu_kernel void @constant_load( 42; RECOV-SAME: i64 [[I:%.*]]) #[[ATTR0:[0-9]+]] { 43; RECOV-NEXT: entry: 44; RECOV-NEXT: [[A:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(4) @x, i64 0, i64 [[I]] 45; RECOV-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(4) [[A]] to i64 46; RECOV-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 47; RECOV-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 48; RECOV-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr 49; RECOV-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 50; RECOV-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 51; RECOV-NEXT: [[TMP6:%.*]] = and i64 [[TMP0]], 7 52; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 3 53; RECOV-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i8 54; RECOV-NEXT: [[TMP9:%.*]] = icmp sge i8 [[TMP8]], [[TMP4]] 55; RECOV-NEXT: [[TMP10:%.*]] = and i1 [[TMP5]], [[TMP9]] 56; RECOV-NEXT: br i1 [[TMP10]], label [[ASAN_REPORT:%.*]], label [[TMP11:%.*]], !prof [[PROF2:![0-9]+]] 57; RECOV: asan.report: 58; RECOV-NEXT: call void @__asan_report_load4_noabort(i64 [[TMP0]]) #[[ATTR3:[0-9]+]] 59; RECOV-NEXT: br label [[TMP11]] 60; RECOV: 11: 61; RECOV-NEXT: [[Q:%.*]] = load i32, ptr addrspace(4) [[A]], align 4 62; RECOV-NEXT: ret void 63; 64entry: 65 %a = getelementptr inbounds [2 x i32], ptr addrspace(4) @x, i64 0, i64 %i 66 %q = load i32, ptr addrspace(4) %a, align 4 67 ret void 68} 69 70define protected amdgpu_kernel void @constant_load_8(i64 %i) sanitize_address { 71; CHECK-LABEL: define protected amdgpu_kernel void @constant_load_8( 72; CHECK-SAME: i64 [[I:%.*]]) #[[ATTR0]] { 73; CHECK-NEXT: entry: 74; CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [2 x i64], ptr addrspace(4) @x8, i64 0, i64 [[I]] 75; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(4) [[A]] to i64 76; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 77; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 78; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr 79; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 80; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 81; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP5]]) 82; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP6]], 0 83; CHECK-NEXT: br i1 [[TMP7]], label [[ASAN_REPORT:%.*]], label [[TMP10:%.*]], !prof [[PROF2]] 84; CHECK: asan.report: 85; CHECK-NEXT: br i1 [[TMP5]], label [[TMP8:%.*]], label [[TMP9:%.*]] 86; CHECK: 8: 87; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP0]]) #[[ATTR5]] 88; CHECK-NEXT: call void @llvm.amdgcn.unreachable() 89; CHECK-NEXT: br label [[TMP9]] 90; CHECK: 9: 91; CHECK-NEXT: br label [[TMP10]] 92; CHECK: 10: 93; CHECK-NEXT: [[Q:%.*]] = load i64, ptr addrspace(4) [[A]], align 8 94; CHECK-NEXT: ret void 95; 96; RECOV-LABEL: define protected amdgpu_kernel void @constant_load_8( 97; RECOV-SAME: i64 [[I:%.*]]) #[[ATTR0]] { 98; RECOV-NEXT: entry: 99; RECOV-NEXT: [[A:%.*]] = getelementptr inbounds [2 x i64], ptr addrspace(4) @x8, i64 0, i64 [[I]] 100; RECOV-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(4) [[A]] to i64 101; RECOV-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3 102; RECOV-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880 103; RECOV-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr 104; RECOV-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 105; RECOV-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0 106; RECOV-NEXT: br i1 [[TMP5]], label [[ASAN_REPORT:%.*]], label [[TMP6:%.*]], !prof [[PROF2]] 107; RECOV: asan.report: 108; RECOV-NEXT: call void @__asan_report_load8_noabort(i64 [[TMP0]]) #[[ATTR3]] 109; RECOV-NEXT: br label [[TMP6]] 110; RECOV: 6: 111; RECOV-NEXT: [[Q:%.*]] = load i64, ptr addrspace(4) [[A]], align 8 112; RECOV-NEXT: ret void 113; 114entry: 115 %a = getelementptr inbounds [2 x i64], ptr addrspace(4) @x8, i64 0, i64 %i 116 %q = load i64, ptr addrspace(4) %a, align 8 117 ret void 118} 119