1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt %loadexampleirtransforms -passes=tut-simplifycfg -tut-simplifycfg-version=v1 < %s -S -verify-dom-info | FileCheck %s
3; RUN: opt %loadexampleirtransforms -passes=tut-simplifycfg -tut-simplifycfg-version=v2 < %s -S -verify-dom-info | FileCheck %s
4; RUN: opt %loadexampleirtransforms -passes=tut-simplifycfg -tut-simplifycfg-version=v3 < %s -S -verify-dom-info | FileCheck %s
5
6define void @test() {
7; CHECK-LABEL: @test(
8; CHECK-NEXT:  entry:
9; CHECK-NEXT:    switch i32 undef, label [[SW_DEFAULT23:%.*]] [
10; CHECK-NEXT:    i32 129, label [[SW_BB:%.*]]
11; CHECK-NEXT:    i32 215, label [[SW_BB1:%.*]]
12; CHECK-NEXT:    i32 117, label [[SW_BB1]]
13; CHECK-NEXT:    i32 207, label [[SW_BB1]]
14; CHECK-NEXT:    i32 158, label [[SW_BB1]]
15; CHECK-NEXT:    i32 94, label [[SW_BB1]]
16; CHECK-NEXT:    i32 219, label [[SW_BB1]]
17; CHECK-NEXT:    i32 88, label [[SW_BB1]]
18; CHECK-NEXT:    i32 168, label [[SW_BB1]]
19; CHECK-NEXT:    i32 295, label [[SW_BB1]]
20; CHECK-NEXT:    i32 294, label [[SW_BB1]]
21; CHECK-NEXT:    i32 296, label [[SW_BB1]]
22; CHECK-NEXT:    i32 67, label [[SW_BB1]]
23; CHECK-NEXT:    i32 293, label [[SW_BB1]]
24; CHECK-NEXT:    i32 382, label [[SW_BB1]]
25; CHECK-NEXT:    i32 335, label [[SW_BB1]]
26; CHECK-NEXT:    i32 393, label [[SW_BB1]]
27; CHECK-NEXT:    i32 415, label [[SW_BB1]]
28; CHECK-NEXT:    i32 400, label [[SW_BB1]]
29; CHECK-NEXT:    i32 383, label [[SW_BB1]]
30; CHECK-NEXT:    i32 421, label [[SW_BB1]]
31; CHECK-NEXT:    i32 422, label [[SW_BB1]]
32; CHECK-NEXT:    i32 302, label [[SW_BB1]]
33; CHECK-NEXT:    i32 303, label [[SW_BB1]]
34; CHECK-NEXT:    i32 304, label [[SW_BB1]]
35; CHECK-NEXT:    i32 420, label [[SW_BB1]]
36; CHECK-NEXT:    i32 401, label [[SW_EPILOG24:%.*]]
37; CHECK-NEXT:    i32 53, label [[SW_BB12:%.*]]
38; CHECK-NEXT:    i32 44, label [[SW_BB12]]
39; CHECK-NEXT:    ]
40; CHECK:       sw.bb:
41; CHECK-NEXT:    unreachable
42; CHECK:       sw.bb1:
43; CHECK-NEXT:    br label [[SW_EPILOG24]]
44; CHECK:       sw.bb12:
45; CHECK-NEXT:    switch i32 undef, label [[SW_DEFAULT:%.*]] [
46; CHECK-NEXT:    i32 47, label [[SW_BB13:%.*]]
47; CHECK-NEXT:    i32 8, label [[SW_BB13]]
48; CHECK-NEXT:    ]
49; CHECK:       sw.bb13:
50; CHECK-NEXT:    unreachable
51; CHECK:       sw.default:
52; CHECK-NEXT:    unreachable
53; CHECK:       sw.default23:
54; CHECK-NEXT:    unreachable
55; CHECK:       sw.epilog24:
56; CHECK-NEXT:    [[PREVIOUS_3:%.*]] = phi i32 [ undef, [[SW_BB1]] ], [ 401, [[ENTRY:%.*]] ]
57; CHECK-NEXT:    unreachable
58;
59entry:
60  br label %while.body
61
62while.body:                                       ; preds = %entry
63  switch i32 undef, label %sw.default23 [
64  i32 129, label %sw.bb
65  i32 215, label %sw.bb1
66  i32 117, label %sw.bb1
67  i32 207, label %sw.bb1
68  i32 158, label %sw.bb1
69  i32 94, label %sw.bb1
70  i32 219, label %sw.bb1
71  i32 88, label %sw.bb1
72  i32 168, label %sw.bb1
73  i32 295, label %sw.bb1
74  i32 294, label %sw.bb1
75  i32 296, label %sw.bb1
76  i32 67, label %sw.bb1
77  i32 293, label %sw.bb1
78  i32 382, label %sw.bb1
79  i32 335, label %sw.bb1
80  i32 393, label %sw.bb1
81  i32 415, label %sw.bb1
82  i32 400, label %sw.bb1
83  i32 383, label %sw.bb1
84  i32 421, label %sw.bb1
85  i32 422, label %sw.bb1
86  i32 302, label %sw.bb1
87  i32 303, label %sw.bb1
88  i32 304, label %sw.bb1
89  i32 420, label %sw.bb1
90  i32 401, label %sw.epilog24
91  i32 53, label %sw.bb12
92  i32 44, label %sw.bb12
93  ]
94
95sw.bb:                                            ; preds = %while.body
96  unreachable
97
98sw.bb1:                                           ; preds = %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body, %while.body
99  br i1 false, label %land.lhs.true, label %sw.epilog24
100
101land.lhs.true:                                    ; preds = %sw.bb1
102  br label %sw.epilog24
103
104sw.bb12:                                          ; preds = %while.body, %while.body
105  switch i32 undef, label %sw.default [
106  i32 47, label %sw.bb13
107  i32 8, label %sw.bb13
108  ]
109
110sw.bb13:                                          ; preds = %sw.bb12, %sw.bb12
111  unreachable
112
113sw.default:                                       ; preds = %sw.bb12
114  unreachable
115
116sw.default23:                                     ; preds = %while.body
117  unreachable
118
119sw.epilog24:                                      ; preds = %land.lhs.true, %sw.bb1, %while.body
120  %Previous.3 = phi i32 [ undef, %land.lhs.true ], [ undef, %sw.bb1 ], [ 401, %while.body ]
121  unreachable
122}
123