1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=X86 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64 4 5define i32 @i32_zext_shift_i16_zext_i1(i1 %a0) nounwind { 6; X86-LABEL: i32_zext_shift_i16_zext_i1: 7; X86: # %bb.0: 8; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax 9; X86-NEXT: andl $1, %eax 10; X86-NEXT: shll $5, %eax 11; X86-NEXT: retl 12; 13; X64-LABEL: i32_zext_shift_i16_zext_i1: 14; X64: # %bb.0: 15; X64-NEXT: movl %edi, %eax 16; X64-NEXT: andl $1, %eax 17; X64-NEXT: shll $5, %eax 18; X64-NEXT: retq 19 %t0 = zext i1 %a0 to i16 20 %t1 = shl i16 %t0, 5 21 %t2 = zext i16 %t1 to i32 22 ret i32 %t2 23} 24 25define i32 @i32_zext_shift_i16_zext_i8(i8 %a0) nounwind { 26; X86-LABEL: i32_zext_shift_i16_zext_i8: 27; X86: # %bb.0: 28; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax 29; X86-NEXT: shll $5, %eax 30; X86-NEXT: retl 31; 32; X64-LABEL: i32_zext_shift_i16_zext_i8: 33; X64: # %bb.0: 34; X64-NEXT: movzbl %dil, %eax 35; X64-NEXT: shll $5, %eax 36; X64-NEXT: retq 37 %t0 = zext i8 %a0 to i16 38 %t1 = shl i16 %t0, 5 39 %t2 = zext i16 %t1 to i32 40 ret i32 %t2 41} 42 43define i64 @i64_zext_shift_i16_zext_i8(i8 %a0) nounwind { 44; X86-LABEL: i64_zext_shift_i16_zext_i8: 45; X86: # %bb.0: 46; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax 47; X86-NEXT: shll $5, %eax 48; X86-NEXT: xorl %edx, %edx 49; X86-NEXT: retl 50; 51; X64-LABEL: i64_zext_shift_i16_zext_i8: 52; X64: # %bb.0: 53; X64-NEXT: movzbl %dil, %eax 54; X64-NEXT: shll $5, %eax 55; X64-NEXT: retq 56 %t0 = zext i8 %a0 to i16 57 %t1 = shl i16 %t0, 5 58 %t2 = zext i16 %t1 to i64 59 ret i64 %t2 60} 61 62define i64 @i64_zext_shift_i32_zext_i8(i8 %a0) nounwind { 63; X86-LABEL: i64_zext_shift_i32_zext_i8: 64; X86: # %bb.0: 65; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax 66; X86-NEXT: shll $3, %eax 67; X86-NEXT: xorl %edx, %edx 68; X86-NEXT: retl 69; 70; X64-LABEL: i64_zext_shift_i32_zext_i8: 71; X64: # %bb.0: 72; X64-NEXT: movzbl %dil, %eax 73; X64-NEXT: shll $3, %eax 74; X64-NEXT: retq 75 %t0 = zext i8 %a0 to i32 76 %t1 = shl i32 %t0, 3 77 %t2 = zext i32 %t1 to i64 78 ret i64 %t2 79} 80 81define i64 @i64_zext_shift_i32_zext_i16(i16 %a0) nounwind { 82; X86-LABEL: i64_zext_shift_i32_zext_i16: 83; X86: # %bb.0: 84; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax 85; X86-NEXT: shll $5, %eax 86; X86-NEXT: xorl %edx, %edx 87; X86-NEXT: retl 88; 89; X64-LABEL: i64_zext_shift_i32_zext_i16: 90; X64: # %bb.0: 91; X64-NEXT: movzwl %di, %eax 92; X64-NEXT: shll $5, %eax 93; X64-NEXT: retq 94 %t0 = zext i16 %a0 to i32 95 %t1 = shl i32 %t0, 5 96 %t2 = zext i32 %t1 to i64 97 ret i64 %t2 98} 99 100define i128 @i128_zext_shift_i64_zext_i8(i8 %a0) nounwind { 101; X86-LABEL: i128_zext_shift_i64_zext_i8: 102; X86: # %bb.0: 103; X86-NEXT: movl {{[0-9]+}}(%esp), %eax 104; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx 105; X86-NEXT: shll $4, %ecx 106; X86-NEXT: movl %ecx, (%eax) 107; X86-NEXT: movl $0, 12(%eax) 108; X86-NEXT: movl $0, 8(%eax) 109; X86-NEXT: movl $0, 4(%eax) 110; X86-NEXT: retl $4 111; 112; X64-LABEL: i128_zext_shift_i64_zext_i8: 113; X64: # %bb.0: 114; X64-NEXT: movzbl %dil, %eax 115; X64-NEXT: shll $4, %eax 116; X64-NEXT: xorl %edx, %edx 117; X64-NEXT: retq 118 %t0 = zext i8 %a0 to i64 119 %t1 = shl i64 %t0, 4 120 %t2 = zext i64 %t1 to i128 121 ret i128 %t2 122} 123 124define i128 @i128_zext_shift_i64_zext_i16(i16 %a0) nounwind { 125; X86-LABEL: i128_zext_shift_i64_zext_i16: 126; X86: # %bb.0: 127; X86-NEXT: movl {{[0-9]+}}(%esp), %eax 128; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx 129; X86-NEXT: shll $7, %ecx 130; X86-NEXT: movl %ecx, (%eax) 131; X86-NEXT: movl $0, 12(%eax) 132; X86-NEXT: movl $0, 8(%eax) 133; X86-NEXT: movl $0, 4(%eax) 134; X86-NEXT: retl $4 135; 136; X64-LABEL: i128_zext_shift_i64_zext_i16: 137; X64: # %bb.0: 138; X64-NEXT: movzwl %di, %eax 139; X64-NEXT: shll $7, %eax 140; X64-NEXT: xorl %edx, %edx 141; X64-NEXT: retq 142 %t0 = zext i16 %a0 to i64 143 %t1 = shl i64 %t0,7 144 %t2 = zext i64 %t1 to i128 145 ret i128 %t2 146} 147