1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=CHECK,X86 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,X64 4 5define i32 @i32_zext_shift_i16_zext_i1(i1 %a0) nounwind { 6; CHECK-LABEL: i32_zext_shift_i16_zext_i1: 7; CHECK: # %bb.0: 8; CHECK-NEXT: xorl %eax, %eax 9; CHECK-NEXT: ret{{[l|q]}} 10 %t0 = zext i1 %a0 to i16 11 %t1 = lshr i16 %t0, 5 12 %t2 = zext i16 %t1 to i32 13 ret i32 %t2 14} 15 16define i32 @i32_zext_shift_i16_zext_i8(i8 %a0) nounwind { 17; X86-LABEL: i32_zext_shift_i16_zext_i8: 18; X86: # %bb.0: 19; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax 20; X86-NEXT: shrl $5, %eax 21; X86-NEXT: retl 22; 23; X64-LABEL: i32_zext_shift_i16_zext_i8: 24; X64: # %bb.0: 25; X64-NEXT: movzbl %dil, %eax 26; X64-NEXT: shrl $5, %eax 27; X64-NEXT: retq 28 %t0 = zext i8 %a0 to i16 29 %t1 = lshr i16 %t0, 5 30 %t2 = zext i16 %t1 to i32 31 ret i32 %t2 32} 33 34define i64 @i64_zext_shift_i16_zext_i8(i8 %a0) nounwind { 35; X86-LABEL: i64_zext_shift_i16_zext_i8: 36; X86: # %bb.0: 37; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax 38; X86-NEXT: shrl $5, %eax 39; X86-NEXT: xorl %edx, %edx 40; X86-NEXT: retl 41; 42; X64-LABEL: i64_zext_shift_i16_zext_i8: 43; X64: # %bb.0: 44; X64-NEXT: movzbl %dil, %eax 45; X64-NEXT: shrl $5, %eax 46; X64-NEXT: retq 47 %t0 = zext i8 %a0 to i16 48 %t1 = lshr i16 %t0, 5 49 %t2 = zext i16 %t1 to i64 50 ret i64 %t2 51} 52 53define i64 @i64_zext_shift_i32_zext_i8(i8 %a0) nounwind { 54; X86-LABEL: i64_zext_shift_i32_zext_i8: 55; X86: # %bb.0: 56; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax 57; X86-NEXT: shrl $3, %eax 58; X86-NEXT: xorl %edx, %edx 59; X86-NEXT: retl 60; 61; X64-LABEL: i64_zext_shift_i32_zext_i8: 62; X64: # %bb.0: 63; X64-NEXT: movzbl %dil, %eax 64; X64-NEXT: shrl $3, %eax 65; X64-NEXT: retq 66 %t0 = zext i8 %a0 to i32 67 %t1 = lshr i32 %t0, 3 68 %t2 = zext i32 %t1 to i64 69 ret i64 %t2 70} 71 72define i64 @i64_zext_shift_i32_zext_i16(i16 %a0) nounwind { 73; X86-LABEL: i64_zext_shift_i32_zext_i16: 74; X86: # %bb.0: 75; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax 76; X86-NEXT: shrl $5, %eax 77; X86-NEXT: xorl %edx, %edx 78; X86-NEXT: retl 79; 80; X64-LABEL: i64_zext_shift_i32_zext_i16: 81; X64: # %bb.0: 82; X64-NEXT: movzwl %di, %eax 83; X64-NEXT: shrl $5, %eax 84; X64-NEXT: retq 85 %t0 = zext i16 %a0 to i32 86 %t1 = lshr i32 %t0, 5 87 %t2 = zext i32 %t1 to i64 88 ret i64 %t2 89} 90 91define i128 @i128_zext_shift_i64_zext_i8(i8 %a0) nounwind { 92; X86-LABEL: i128_zext_shift_i64_zext_i8: 93; X86: # %bb.0: 94; X86-NEXT: movl {{[0-9]+}}(%esp), %eax 95; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx 96; X86-NEXT: shrl $4, %ecx 97; X86-NEXT: movl %ecx, (%eax) 98; X86-NEXT: movl $0, 12(%eax) 99; X86-NEXT: movl $0, 8(%eax) 100; X86-NEXT: movl $0, 4(%eax) 101; X86-NEXT: retl $4 102; 103; X64-LABEL: i128_zext_shift_i64_zext_i8: 104; X64: # %bb.0: 105; X64-NEXT: movzbl %dil, %eax 106; X64-NEXT: shrl $4, %eax 107; X64-NEXT: xorl %edx, %edx 108; X64-NEXT: retq 109 %t0 = zext i8 %a0 to i64 110 %t1 = lshr i64 %t0, 4 111 %t2 = zext i64 %t1 to i128 112 ret i128 %t2 113} 114 115define i128 @i128_zext_shift_i64_zext_i16(i16 %a0) nounwind { 116; X86-LABEL: i128_zext_shift_i64_zext_i16: 117; X86: # %bb.0: 118; X86-NEXT: movl {{[0-9]+}}(%esp), %eax 119; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx 120; X86-NEXT: shrl $7, %ecx 121; X86-NEXT: movl %ecx, (%eax) 122; X86-NEXT: movl $0, 12(%eax) 123; X86-NEXT: movl $0, 8(%eax) 124; X86-NEXT: movl $0, 4(%eax) 125; X86-NEXT: retl $4 126; 127; X64-LABEL: i128_zext_shift_i64_zext_i16: 128; X64: # %bb.0: 129; X64-NEXT: movzwl %di, %eax 130; X64-NEXT: shrl $7, %eax 131; X64-NEXT: xorl %edx, %edx 132; X64-NEXT: retq 133 %t0 = zext i16 %a0 to i64 134 %t1 = lshr i64 %t0,7 135 %t2 = zext i64 %t1 to i128 136 ret i128 %t2 137} 138