xref: /llvm-project/llvm/test/CodeGen/X86/vec_no-common-bits.ll (revision 617ad14060dcdfa9f1f967a3edd9e097de8bf83a) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK
3
4; In the following patterns, lhs and rhs of the or instruction have no common bits.
5; Therefore, "add" and "or" instructions are equal.
6
7define <2 x i32> @or_and_and_rhs_neg_vec_i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
8; CHECK-LABEL: or_and_and_rhs_neg_vec_i32:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    xorps %xmm0, %xmm0
11; CHECK-NEXT:    retq
12  %and1 = and <2 x i32> %z, %y
13  %xor = xor <2 x i32> %y, <i32 -1, i32 -1>
14  %and2 = and <2 x i32> %x, %xor
15  %or = or <2 x i32> %and1, %and2
16  %add = add <2 x i32> %and1, %and2
17  %sub = sub <2 x i32> %or, %add
18  ret <2 x i32> %sub
19}
20
21define <2 x i32> @or_and_and_lhs_neg_vec_i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
22; CHECK-LABEL: or_and_and_lhs_neg_vec_i32:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    xorps %xmm0, %xmm0
25; CHECK-NEXT:    retq
26  %and1 = and <2 x i32> %z, %y
27  %xor = xor <2 x i32> %y, <i32 -1, i32 -1>
28  %and2 = and <2 x i32> %xor, %x
29  %or = or <2 x i32> %and1, %and2
30  %add = add <2 x i32> %and1, %and2
31  %sub = sub <2 x i32> %or, %add
32  ret <2 x i32> %sub
33}
34
35define <2 x i32> @or_and_rhs_neg_and_vec_i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
36; CHECK-LABEL: or_and_rhs_neg_and_vec_i32:
37; CHECK:       # %bb.0:
38; CHECK-NEXT:    xorps %xmm0, %xmm0
39; CHECK-NEXT:    retq
40  %xor = xor <2 x i32> %y, <i32 -1, i32 -1>
41  %and1 = and <2 x i32> %z, %xor
42  %and2 = and <2 x i32> %x, %y
43  %or = or <2 x i32> %and1, %and2
44  %add = add <2 x i32> %and1, %and2
45  %sub = sub <2 x i32> %or, %add
46  ret <2 x i32> %sub
47}
48
49define <2 x i32> @or_and_lhs_neg_and_vec_i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
50; CHECK-LABEL: or_and_lhs_neg_and_vec_i32:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    xorps %xmm0, %xmm0
53; CHECK-NEXT:    retq
54  %xor = xor <2 x i32> %y, <i32 -1, i32 -1>
55  %and1 = and <2 x i32> %xor, %z
56  %and2 = and <2 x i32> %x, %y
57  %or = or <2 x i32> %and1, %and2
58  %add = add <2 x i32> %and1, %and2
59  %sub = sub <2 x i32> %or, %add
60  ret <2 x i32> %sub
61}
62
63define <2 x i64> @or_and_and_rhs_neg_vec_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
64; CHECK-LABEL: or_and_and_rhs_neg_vec_i64:
65; CHECK:       # %bb.0:
66; CHECK-NEXT:    xorps %xmm0, %xmm0
67; CHECK-NEXT:    retq
68  %and1 = and <2 x i64> %z, %y
69  %xor = xor <2 x i64> %y, <i64 -1, i64 -1>
70  %and2 = and <2 x i64> %x, %xor
71  %or = or <2 x i64> %and1, %and2
72  %add = add <2 x i64> %and1, %and2
73  %sub = sub <2 x i64> %or, %add
74  ret <2 x i64> %sub
75}
76
77define <2 x i64> @or_and_and_lhs_neg_vec_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
78; CHECK-LABEL: or_and_and_lhs_neg_vec_i64:
79; CHECK:       # %bb.0:
80; CHECK-NEXT:    xorps %xmm0, %xmm0
81; CHECK-NEXT:    retq
82  %and1 = and <2 x i64> %z, %y
83  %xor = xor <2 x i64> %y, <i64 -1, i64 -1>
84  %and2 = and <2 x i64> %xor, %x
85  %or = or <2 x i64> %and1, %and2
86  %add = add <2 x i64> %and1, %and2
87  %sub = sub <2 x i64> %or, %add
88  ret <2 x i64> %sub
89}
90
91define <2 x i64> @or_and_rhs_neg_and_vec_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
92; CHECK-LABEL: or_and_rhs_neg_and_vec_i64:
93; CHECK:       # %bb.0:
94; CHECK-NEXT:    xorps %xmm0, %xmm0
95; CHECK-NEXT:    retq
96  %xor = xor <2 x i64> %y, <i64 -1, i64 -1>
97  %and1 = and <2 x i64> %z, %xor
98  %and2 = and <2 x i64> %x, %y
99  %or = or <2 x i64> %and1, %and2
100  %add = add <2 x i64> %and1, %and2
101  %sub = sub <2 x i64> %or, %add
102  ret <2 x i64> %sub
103}
104
105define <2 x i64> @or_and_lhs_neg_and_vec_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
106; CHECK-LABEL: or_and_lhs_neg_and_vec_i64:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    xorps %xmm0, %xmm0
109; CHECK-NEXT:    retq
110  %xor = xor <2 x i64> %y, <i64 -1, i64 -1>
111  %and1 = and <2 x i64> %xor, %z
112  %and2 = and <2 x i64> %x, %y
113  %or = or <2 x i64> %and1, %and2
114  %add = add <2 x i64> %and1, %and2
115  %sub = sub <2 x i64> %or, %add
116  ret <2 x i64> %sub
117}
118