xref: /llvm-project/llvm/test/CodeGen/X86/vec_ins_extract-1.ll (revision 43e94b15ea0c180ebb0fd3e6b697dac4564aaf60)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X32
3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X64
4
5; Inserts and extracts with variable indices must be lowered
6; to memory accesses.
7
8define i32 @t0(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
9; X32-LABEL: t0:
10; X32:       # %bb.0:
11; X32-NEXT:    pushl %ebp
12; X32-NEXT:    movl %esp, %ebp
13; X32-NEXT:    andl $-16, %esp
14; X32-NEXT:    subl $32, %esp
15; X32-NEXT:    andl $3, %eax
16; X32-NEXT:    movaps %xmm0, (%esp)
17; X32-NEXT:    movl $76, (%esp,%eax,4)
18; X32-NEXT:    movl (%esp), %eax
19; X32-NEXT:    movl %ebp, %esp
20; X32-NEXT:    popl %ebp
21; X32-NEXT:    retl
22;
23; X64-LABEL: t0:
24; X64:       # %bb.0:
25; X64-NEXT:    # kill: def $edi killed $edi def $rdi
26; X64-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
27; X64-NEXT:    andl $3, %edi
28; X64-NEXT:    movl $76, -24(%rsp,%rdi,4)
29; X64-NEXT:    movl -{{[0-9]+}}(%rsp), %eax
30; X64-NEXT:    retq
31  %t13 = insertelement <4 x i32> %t8, i32 76, i32 %t7
32  %t9 = extractelement <4 x i32> %t13, i32 0
33  ret i32 %t9
34}
35
36define i32 @t1(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
37; X32-LABEL: t1:
38; X32:       # %bb.0:
39; X32-NEXT:    pushl %ebp
40; X32-NEXT:    movl %esp, %ebp
41; X32-NEXT:    andl $-16, %esp
42; X32-NEXT:    subl $32, %esp
43; X32-NEXT:    andl $3, %eax
44; X32-NEXT:    movl $76, %ecx
45; X32-NEXT:    pinsrd $0, %ecx, %xmm0
46; X32-NEXT:    movdqa %xmm0, (%esp)
47; X32-NEXT:    movl (%esp,%eax,4), %eax
48; X32-NEXT:    movl %ebp, %esp
49; X32-NEXT:    popl %ebp
50; X32-NEXT:    retl
51;
52; X64-LABEL: t1:
53; X64:       # %bb.0:
54; X64-NEXT:    # kill: def $edi killed $edi def $rdi
55; X64-NEXT:    movl $76, %eax
56; X64-NEXT:    pinsrd $0, %eax, %xmm0
57; X64-NEXT:    movdqa %xmm0, -{{[0-9]+}}(%rsp)
58; X64-NEXT:    andl $3, %edi
59; X64-NEXT:    movl -24(%rsp,%rdi,4), %eax
60; X64-NEXT:    retq
61  %t13 = insertelement <4 x i32> %t8, i32 76, i32 0
62  %t9 = extractelement <4 x i32> %t13, i32 %t7
63  ret i32 %t9
64}
65
66define <4 x i32> @t2(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
67; X32-LABEL: t2:
68; X32:       # %bb.0:
69; X32-NEXT:    pushl %ebp
70; X32-NEXT:    movl %esp, %ebp
71; X32-NEXT:    andl $-16, %esp
72; X32-NEXT:    subl $32, %esp
73; X32-NEXT:    andl $3, %eax
74; X32-NEXT:    movdqa %xmm0, (%esp)
75; X32-NEXT:    pinsrd $0, (%esp,%eax,4), %xmm0
76; X32-NEXT:    movl %ebp, %esp
77; X32-NEXT:    popl %ebp
78; X32-NEXT:    retl
79;
80; X64-LABEL: t2:
81; X64:       # %bb.0:
82; X64-NEXT:    # kill: def $edi killed $edi def $rdi
83; X64-NEXT:    movdqa %xmm0, -{{[0-9]+}}(%rsp)
84; X64-NEXT:    andl $3, %edi
85; X64-NEXT:    pinsrd $0, -24(%rsp,%rdi,4), %xmm0
86; X64-NEXT:    retq
87  %t9 = extractelement <4 x i32> %t8, i32 %t7
88  %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 0
89  ret <4 x i32> %t13
90}
91
92define <4 x i32> @t3(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
93; X32-LABEL: t3:
94; X32:       # %bb.0:
95; X32-NEXT:    pushl %ebp
96; X32-NEXT:    movl %esp, %ebp
97; X32-NEXT:    andl $-16, %esp
98; X32-NEXT:    subl $32, %esp
99; X32-NEXT:    andl $3, %eax
100; X32-NEXT:    movaps %xmm0, (%esp)
101; X32-NEXT:    movss %xmm0, (%esp,%eax,4)
102; X32-NEXT:    movaps (%esp), %xmm0
103; X32-NEXT:    movl %ebp, %esp
104; X32-NEXT:    popl %ebp
105; X32-NEXT:    retl
106;
107; X64-LABEL: t3:
108; X64:       # %bb.0:
109; X64-NEXT:    # kill: def $edi killed $edi def $rdi
110; X64-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
111; X64-NEXT:    andl $3, %edi
112; X64-NEXT:    movss %xmm0, -24(%rsp,%rdi,4)
113; X64-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm0
114; X64-NEXT:    retq
115  %t9 = extractelement <4 x i32> %t8, i32 0
116  %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 %t7
117  ret <4 x i32> %t13
118}
119