1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+tbm < %s | FileCheck %s 3 4define i32 @test_x86_tbm_bextri_u32(i32 %a) nounwind { 5; CHECK-LABEL: test_x86_tbm_bextri_u32: 6; CHECK: # %bb.0: 7; CHECK-NEXT: bextrl $3076, %edi, %eax # imm = 0xC04 8; CHECK-NEXT: retq 9 %t0 = lshr i32 %a, 4 10 %t1 = and i32 %t0, 4095 11 ret i32 %t1 12} 13 14; Make sure we still use AH subreg trick for extracting bits 15:8 15define i32 @test_x86_tbm_bextri_u32_subreg(i32 %a) nounwind { 16; CHECK-LABEL: test_x86_tbm_bextri_u32_subreg: 17; CHECK: # %bb.0: 18; CHECK-NEXT: movl %edi, %eax 19; CHECK-NEXT: movzbl %ah, %eax 20; CHECK-NEXT: retq 21 %t0 = lshr i32 %a, 8 22 %t1 = and i32 %t0, 255 23 ret i32 %t1 24} 25 26define i32 @test_x86_tbm_bextri_u32_m(ptr nocapture %a) nounwind { 27; CHECK-LABEL: test_x86_tbm_bextri_u32_m: 28; CHECK: # %bb.0: 29; CHECK-NEXT: bextrl $3076, (%rdi), %eax # imm = 0xC04 30; CHECK-NEXT: retq 31 %t0 = load i32, ptr %a 32 %t1 = lshr i32 %t0, 4 33 %t2 = and i32 %t1, 4095 34 ret i32 %t2 35} 36 37define i32 @test_x86_tbm_bextri_u32_z(i32 %a, i32 %b) nounwind { 38; CHECK-LABEL: test_x86_tbm_bextri_u32_z: 39; CHECK: # %bb.0: 40; CHECK-NEXT: bextrl $3076, %edi, %eax # imm = 0xC04 41; CHECK-NEXT: cmovel %esi, %eax 42; CHECK-NEXT: retq 43 %t0 = lshr i32 %a, 4 44 %t1 = and i32 %t0, 4095 45 %t2 = icmp eq i32 %t1, 0 46 %t3 = select i1 %t2, i32 %b, i32 %t1 47 ret i32 %t3 48} 49 50define i32 @test_x86_tbm_bextri_u32_z2(i32 %a, i32 %b, i32 %c) nounwind { 51; CHECK-LABEL: test_x86_tbm_bextri_u32_z2: 52; CHECK: # %bb.0: 53; CHECK-NEXT: movl %esi, %eax 54; CHECK-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04 55; CHECK-NEXT: cmovnel %edx, %eax 56; CHECK-NEXT: retq 57 %t0 = lshr i32 %a, 4 58 %t1 = and i32 %t0, 4095 59 %t2 = icmp eq i32 %t1, 0 60 %t3 = select i1 %t2, i32 %b, i32 %c 61 ret i32 %t3 62} 63 64define i32 @test_x86_tbm_bextri_u32_sle(i32 %a, i32 %b, i32 %c) nounwind { 65; CHECK-LABEL: test_x86_tbm_bextri_u32_sle: 66; CHECK: # %bb.0: 67; CHECK-NEXT: movl %esi, %eax 68; CHECK-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04 69; CHECK-NEXT: testl %ecx, %ecx 70; CHECK-NEXT: cmovgl %edx, %eax 71; CHECK-NEXT: retq 72 %t0 = lshr i32 %a, 4 73 %t1 = and i32 %t0, 4095 74 %t2 = icmp sle i32 %t1, 0 75 %t3 = select i1 %t2, i32 %b, i32 %c 76 ret i32 %t3 77} 78 79define i64 @test_x86_tbm_bextri_u64(i64 %a) nounwind { 80; CHECK-LABEL: test_x86_tbm_bextri_u64: 81; CHECK: # %bb.0: 82; CHECK-NEXT: bextrl $3076, %edi, %eax # imm = 0xC04 83; CHECK-NEXT: retq 84 %t0 = lshr i64 %a, 4 85 %t1 = and i64 %t0, 4095 86 ret i64 %t1 87} 88 89; Make sure we still use AH subreg trick for extracting bits 15:8 90define i64 @test_x86_tbm_bextri_u64_subreg(i64 %a) nounwind { 91; CHECK-LABEL: test_x86_tbm_bextri_u64_subreg: 92; CHECK: # %bb.0: 93; CHECK-NEXT: movq %rdi, %rax 94; CHECK-NEXT: movzbl %ah, %eax 95; CHECK-NEXT: retq 96 %t0 = lshr i64 %a, 8 97 %t1 = and i64 %t0, 255 98 ret i64 %t1 99} 100 101define i64 @test_x86_tbm_bextri_u64_m(ptr nocapture %a) nounwind { 102; CHECK-LABEL: test_x86_tbm_bextri_u64_m: 103; CHECK: # %bb.0: 104; CHECK-NEXT: bextrl $3076, (%rdi), %eax # imm = 0xC04 105; CHECK-NEXT: retq 106 %t0 = load i64, ptr %a 107 %t1 = lshr i64 %t0, 4 108 %t2 = and i64 %t1, 4095 109 ret i64 %t2 110} 111 112define i64 @test_x86_tbm_bextri_u64_z(i64 %a, i64 %b) nounwind { 113; CHECK-LABEL: test_x86_tbm_bextri_u64_z: 114; CHECK: # %bb.0: 115; CHECK-NEXT: bextrl $3076, %edi, %eax # imm = 0xC04 116; CHECK-NEXT: cmoveq %rsi, %rax 117; CHECK-NEXT: retq 118 %t0 = lshr i64 %a, 4 119 %t1 = and i64 %t0, 4095 120 %t2 = icmp eq i64 %t1, 0 121 %t3 = select i1 %t2, i64 %b, i64 %t1 122 ret i64 %t3 123} 124 125define i64 @test_x86_tbm_bextri_u64_z2(i64 %a, i64 %b, i64 %c) nounwind { 126; CHECK-LABEL: test_x86_tbm_bextri_u64_z2: 127; CHECK: # %bb.0: 128; CHECK-NEXT: movq %rsi, %rax 129; CHECK-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04 130; CHECK-NEXT: cmovneq %rdx, %rax 131; CHECK-NEXT: retq 132 %t0 = lshr i64 %a, 4 133 %t1 = and i64 %t0, 4095 134 %t2 = icmp eq i64 %t1, 0 135 %t3 = select i1 %t2, i64 %b, i64 %c 136 ret i64 %t3 137} 138 139define i64 @test_x86_tbm_bextri_u64_sle(i64 %a, i64 %b, i64 %c) nounwind { 140; CHECK-LABEL: test_x86_tbm_bextri_u64_sle: 141; CHECK: # %bb.0: 142; CHECK-NEXT: movq %rsi, %rax 143; CHECK-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04 144; CHECK-NEXT: testq %rcx, %rcx 145; CHECK-NEXT: cmovgq %rdx, %rax 146; CHECK-NEXT: retq 147 %t0 = lshr i64 %a, 4 148 %t1 = and i64 %t0, 4095 149 %t2 = icmp sle i64 %t1, 0 150 %t3 = select i1 %t2, i64 %b, i64 %c 151 ret i64 %t3 152} 153 154define i32 @test_x86_tbm_blcfill_u32(i32 %a) nounwind { 155; CHECK-LABEL: test_x86_tbm_blcfill_u32: 156; CHECK: # %bb.0: 157; CHECK-NEXT: blcfilll %edi, %eax 158; CHECK-NEXT: retq 159 %t0 = add i32 %a, 1 160 %t1 = and i32 %t0, %a 161 ret i32 %t1 162} 163 164define i32 @test_x86_tbm_blcfill_u32_z(i32 %a, i32 %b) nounwind { 165; CHECK-LABEL: test_x86_tbm_blcfill_u32_z: 166; CHECK: # %bb.0: 167; CHECK-NEXT: blcfilll %edi, %eax 168; CHECK-NEXT: cmovel %esi, %eax 169; CHECK-NEXT: retq 170 %t0 = add i32 %a, 1 171 %t1 = and i32 %t0, %a 172 %t2 = icmp eq i32 %t1, 0 173 %t3 = select i1 %t2, i32 %b, i32 %t1 174 ret i32 %t3 175} 176 177define i32 @test_x86_tbm_blcfill_u32_z2(i32 %a, i32 %b, i32 %c) nounwind { 178; CHECK-LABEL: test_x86_tbm_blcfill_u32_z2: 179; CHECK: # %bb.0: 180; CHECK-NEXT: movl %esi, %eax 181; CHECK-NEXT: blcfilll %edi, %ecx 182; CHECK-NEXT: cmovnel %edx, %eax 183; CHECK-NEXT: retq 184 %t0 = add i32 %a, 1 185 %t1 = and i32 %t0, %a 186 %t2 = icmp eq i32 %t1, 0 187 %t3 = select i1 %t2, i32 %b, i32 %c 188 ret i32 %t3 189} 190 191define i32 @test_x86_tbm_blcfill_u32_sle(i32 %a, i32 %b, i32 %c) nounwind { 192; CHECK-LABEL: test_x86_tbm_blcfill_u32_sle: 193; CHECK: # %bb.0: 194; CHECK-NEXT: movl %esi, %eax 195; CHECK-NEXT: blcfilll %edi, %ecx 196; CHECK-NEXT: cmovgl %edx, %eax 197; CHECK-NEXT: retq 198 %t0 = add i32 %a, 1 199 %t1 = and i32 %t0, %a 200 %t2 = icmp sle i32 %t1, 0 201 %t3 = select i1 %t2, i32 %b, i32 %c 202 ret i32 %t3 203} 204 205define i64 @test_x86_tbm_blcfill_u64(i64 %a) nounwind { 206; CHECK-LABEL: test_x86_tbm_blcfill_u64: 207; CHECK: # %bb.0: 208; CHECK-NEXT: blcfillq %rdi, %rax 209; CHECK-NEXT: retq 210 %t0 = add i64 %a, 1 211 %t1 = and i64 %t0, %a 212 ret i64 %t1 213} 214 215define i64 @test_x86_tbm_blcfill_u64_z(i64 %a, i64 %b) nounwind { 216; CHECK-LABEL: test_x86_tbm_blcfill_u64_z: 217; CHECK: # %bb.0: 218; CHECK-NEXT: blcfillq %rdi, %rax 219; CHECK-NEXT: cmoveq %rsi, %rax 220; CHECK-NEXT: retq 221 %t0 = add i64 %a, 1 222 %t1 = and i64 %t0, %a 223 %t2 = icmp eq i64 %t1, 0 224 %t3 = select i1 %t2, i64 %b, i64 %t1 225 ret i64 %t3 226} 227 228define i64 @test_x86_tbm_blcfill_u64_z2(i64 %a, i64 %b, i64 %c) nounwind { 229; CHECK-LABEL: test_x86_tbm_blcfill_u64_z2: 230; CHECK: # %bb.0: 231; CHECK-NEXT: movq %rsi, %rax 232; CHECK-NEXT: blcfillq %rdi, %rcx 233; CHECK-NEXT: cmovneq %rdx, %rax 234; CHECK-NEXT: retq 235 %t0 = add i64 %a, 1 236 %t1 = and i64 %t0, %a 237 %t2 = icmp eq i64 %t1, 0 238 %t3 = select i1 %t2, i64 %b, i64 %c 239 ret i64 %t3 240} 241 242define i64 @test_x86_tbm_blcfill_u64_sle(i64 %a, i64 %b, i64 %c) nounwind { 243; CHECK-LABEL: test_x86_tbm_blcfill_u64_sle: 244; CHECK: # %bb.0: 245; CHECK-NEXT: movq %rsi, %rax 246; CHECK-NEXT: blcfillq %rdi, %rcx 247; CHECK-NEXT: cmovgq %rdx, %rax 248; CHECK-NEXT: retq 249 %t0 = add i64 %a, 1 250 %t1 = and i64 %t0, %a 251 %t2 = icmp sle i64 %t1, 0 252 %t3 = select i1 %t2, i64 %b, i64 %c 253 ret i64 %t3 254} 255 256define i32 @test_x86_tbm_blci_u32(i32 %a) nounwind { 257; CHECK-LABEL: test_x86_tbm_blci_u32: 258; CHECK: # %bb.0: 259; CHECK-NEXT: blcil %edi, %eax 260; CHECK-NEXT: retq 261 %t0 = add i32 1, %a 262 %t1 = xor i32 %t0, -1 263 %t2 = or i32 %t1, %a 264 ret i32 %t2 265} 266 267define i32 @test_x86_tbm_blci_u32_z(i32 %a, i32 %b) nounwind { 268; CHECK-LABEL: test_x86_tbm_blci_u32_z: 269; CHECK: # %bb.0: 270; CHECK-NEXT: blcil %edi, %eax 271; CHECK-NEXT: cmovel %esi, %eax 272; CHECK-NEXT: retq 273 %t0 = add i32 1, %a 274 %t1 = xor i32 %t0, -1 275 %t2 = or i32 %t1, %a 276 %t3 = icmp eq i32 %t2, 0 277 %t4 = select i1 %t3, i32 %b, i32 %t2 278 ret i32 %t4 279} 280 281define i32 @test_x86_tbm_blci_u32_z2(i32 %a, i32 %b, i32 %c) nounwind { 282; CHECK-LABEL: test_x86_tbm_blci_u32_z2: 283; CHECK: # %bb.0: 284; CHECK-NEXT: movl %esi, %eax 285; CHECK-NEXT: blcil %edi, %ecx 286; CHECK-NEXT: cmovnel %edx, %eax 287; CHECK-NEXT: retq 288 %t0 = add i32 1, %a 289 %t1 = xor i32 %t0, -1 290 %t2 = or i32 %t1, %a 291 %t3 = icmp eq i32 %t2, 0 292 %t4 = select i1 %t3, i32 %b, i32 %c 293 ret i32 %t4 294} 295 296define i32 @test_x86_tbm_blci_u32_sle(i32 %a, i32 %b, i32 %c) nounwind { 297; CHECK-LABEL: test_x86_tbm_blci_u32_sle: 298; CHECK: # %bb.0: 299; CHECK-NEXT: movl %esi, %eax 300; CHECK-NEXT: blcil %edi, %ecx 301; CHECK-NEXT: cmovgl %edx, %eax 302; CHECK-NEXT: retq 303 %t0 = add i32 1, %a 304 %t1 = xor i32 %t0, -1 305 %t2 = or i32 %t1, %a 306 %t3 = icmp sle i32 %t2, 0 307 %t4 = select i1 %t3, i32 %b, i32 %c 308 ret i32 %t4 309} 310 311define i64 @test_x86_tbm_blci_u64(i64 %a) nounwind { 312; CHECK-LABEL: test_x86_tbm_blci_u64: 313; CHECK: # %bb.0: 314; CHECK-NEXT: blciq %rdi, %rax 315; CHECK-NEXT: retq 316 %t0 = add i64 1, %a 317 %t1 = xor i64 %t0, -1 318 %t2 = or i64 %t1, %a 319 ret i64 %t2 320} 321 322define i64 @test_x86_tbm_blci_u64_z(i64 %a, i64 %b) nounwind { 323; CHECK-LABEL: test_x86_tbm_blci_u64_z: 324; CHECK: # %bb.0: 325; CHECK-NEXT: blciq %rdi, %rax 326; CHECK-NEXT: cmoveq %rsi, %rax 327; CHECK-NEXT: retq 328 %t0 = add i64 1, %a 329 %t1 = xor i64 %t0, -1 330 %t2 = or i64 %t1, %a 331 %t3 = icmp eq i64 %t2, 0 332 %t4 = select i1 %t3, i64 %b, i64 %t2 333 ret i64 %t4 334} 335 336define i64 @test_x86_tbm_blci_u64_z2(i64 %a, i64 %b, i64 %c) nounwind { 337; CHECK-LABEL: test_x86_tbm_blci_u64_z2: 338; CHECK: # %bb.0: 339; CHECK-NEXT: movq %rsi, %rax 340; CHECK-NEXT: blciq %rdi, %rcx 341; CHECK-NEXT: cmovneq %rdx, %rax 342; CHECK-NEXT: retq 343 %t0 = add i64 1, %a 344 %t1 = xor i64 %t0, -1 345 %t2 = or i64 %t1, %a 346 %t3 = icmp eq i64 %t2, 0 347 %t4 = select i1 %t3, i64 %b, i64 %c 348 ret i64 %t4 349} 350 351define i64 @test_x86_tbm_blci_u64_sle(i64 %a, i64 %b, i64 %c) nounwind { 352; CHECK-LABEL: test_x86_tbm_blci_u64_sle: 353; CHECK: # %bb.0: 354; CHECK-NEXT: movq %rsi, %rax 355; CHECK-NEXT: blciq %rdi, %rcx 356; CHECK-NEXT: cmovgq %rdx, %rax 357; CHECK-NEXT: retq 358 %t0 = add i64 1, %a 359 %t1 = xor i64 %t0, -1 360 %t2 = or i64 %t1, %a 361 %t3 = icmp sle i64 %t2, 0 362 %t4 = select i1 %t3, i64 %b, i64 %c 363 ret i64 %t4 364} 365 366define i32 @test_x86_tbm_blci_u32_b(i32 %a) nounwind { 367; CHECK-LABEL: test_x86_tbm_blci_u32_b: 368; CHECK: # %bb.0: 369; CHECK-NEXT: blcil %edi, %eax 370; CHECK-NEXT: retq 371 %t0 = sub i32 -2, %a 372 %t1 = or i32 %t0, %a 373 ret i32 %t1 374} 375 376define i64 @test_x86_tbm_blci_u64_b(i64 %a) nounwind { 377; CHECK-LABEL: test_x86_tbm_blci_u64_b: 378; CHECK: # %bb.0: 379; CHECK-NEXT: blciq %rdi, %rax 380; CHECK-NEXT: retq 381 %t0 = sub i64 -2, %a 382 %t1 = or i64 %t0, %a 383 ret i64 %t1 384} 385 386define i32 @test_x86_tbm_blcic_u32(i32 %a) nounwind { 387; CHECK-LABEL: test_x86_tbm_blcic_u32: 388; CHECK: # %bb.0: 389; CHECK-NEXT: blcicl %edi, %eax 390; CHECK-NEXT: retq 391 %t0 = xor i32 %a, -1 392 %t1 = add i32 %a, 1 393 %t2 = and i32 %t1, %t0 394 ret i32 %t2 395} 396 397define i32 @test_x86_tbm_blcic_u32_z(i32 %a, i32 %b) nounwind { 398; CHECK-LABEL: test_x86_tbm_blcic_u32_z: 399; CHECK: # %bb.0: 400; CHECK-NEXT: blcicl %edi, %eax 401; CHECK-NEXT: cmovel %esi, %eax 402; CHECK-NEXT: retq 403 %t0 = xor i32 %a, -1 404 %t1 = add i32 %a, 1 405 %t2 = and i32 %t1, %t0 406 %t3 = icmp eq i32 %t2, 0 407 %t4 = select i1 %t3, i32 %b, i32 %t2 408 ret i32 %t4 409} 410 411define i32 @test_x86_tbm_blcic_u32_z2(i32 %a, i32 %b, i32 %c) nounwind { 412; CHECK-LABEL: test_x86_tbm_blcic_u32_z2: 413; CHECK: # %bb.0: 414; CHECK-NEXT: movl %esi, %eax 415; CHECK-NEXT: blcicl %edi, %ecx 416; CHECK-NEXT: cmovnel %edx, %eax 417; CHECK-NEXT: retq 418 %t0 = xor i32 %a, -1 419 %t1 = add i32 %a, 1 420 %t2 = and i32 %t1, %t0 421 %t3 = icmp eq i32 %t2, 0 422 %t4 = select i1 %t3, i32 %b, i32 %c 423 ret i32 %t4 424} 425 426define i32 @test_x86_tbm_blcic_u32_sle(i32 %a, i32 %b, i32 %c) nounwind { 427; CHECK-LABEL: test_x86_tbm_blcic_u32_sle: 428; CHECK: # %bb.0: 429; CHECK-NEXT: movl %esi, %eax 430; CHECK-NEXT: blcicl %edi, %ecx 431; CHECK-NEXT: cmovgl %edx, %eax 432; CHECK-NEXT: retq 433 %t0 = xor i32 %a, -1 434 %t1 = add i32 %a, 1 435 %t2 = and i32 %t1, %t0 436 %t3 = icmp sle i32 %t2, 0 437 %t4 = select i1 %t3, i32 %b, i32 %c 438 ret i32 %t4 439} 440 441define i64 @test_x86_tbm_blcic_u64(i64 %a) nounwind { 442; CHECK-LABEL: test_x86_tbm_blcic_u64: 443; CHECK: # %bb.0: 444; CHECK-NEXT: blcicq %rdi, %rax 445; CHECK-NEXT: retq 446 %t0 = xor i64 %a, -1 447 %t1 = add i64 %a, 1 448 %t2 = and i64 %t1, %t0 449 ret i64 %t2 450} 451 452define i64 @test_x86_tbm_blcic_u64_z(i64 %a, i64 %b) nounwind { 453; CHECK-LABEL: test_x86_tbm_blcic_u64_z: 454; CHECK: # %bb.0: 455; CHECK-NEXT: blcicq %rdi, %rax 456; CHECK-NEXT: cmoveq %rsi, %rax 457; CHECK-NEXT: retq 458 %t0 = xor i64 %a, -1 459 %t1 = add i64 %a, 1 460 %t2 = and i64 %t1, %t0 461 %t3 = icmp eq i64 %t2, 0 462 %t4 = select i1 %t3, i64 %b, i64 %t2 463 ret i64 %t4 464} 465 466define i64 @test_x86_tbm_blcic_u64_z2(i64 %a, i64 %b, i64 %c) nounwind { 467; CHECK-LABEL: test_x86_tbm_blcic_u64_z2: 468; CHECK: # %bb.0: 469; CHECK-NEXT: movq %rsi, %rax 470; CHECK-NEXT: blcicq %rdi, %rcx 471; CHECK-NEXT: cmovneq %rdx, %rax 472; CHECK-NEXT: retq 473 %t0 = xor i64 %a, -1 474 %t1 = add i64 %a, 1 475 %t2 = and i64 %t1, %t0 476 %t3 = icmp eq i64 %t2, 0 477 %t4 = select i1 %t3, i64 %b, i64 %c 478 ret i64 %t4 479} 480 481define i64 @test_x86_tbm_blcic_u64_sle(i64 %a, i64 %b, i64 %c) nounwind { 482; CHECK-LABEL: test_x86_tbm_blcic_u64_sle: 483; CHECK: # %bb.0: 484; CHECK-NEXT: movq %rsi, %rax 485; CHECK-NEXT: blcicq %rdi, %rcx 486; CHECK-NEXT: cmovgq %rdx, %rax 487; CHECK-NEXT: retq 488 %t0 = xor i64 %a, -1 489 %t1 = add i64 %a, 1 490 %t2 = and i64 %t1, %t0 491 %t3 = icmp sle i64 %t2, 0 492 %t4 = select i1 %t3, i64 %b, i64 %c 493 ret i64 %t4 494} 495 496define i32 @test_x86_tbm_blcmsk_u32(i32 %a) nounwind { 497; CHECK-LABEL: test_x86_tbm_blcmsk_u32: 498; CHECK: # %bb.0: 499; CHECK-NEXT: blcmskl %edi, %eax 500; CHECK-NEXT: retq 501 %t0 = add i32 %a, 1 502 %t1 = xor i32 %t0, %a 503 ret i32 %t1 504} 505 506define i32 @test_x86_tbm_blcmsk_u32_z(i32 %a, i32 %b) nounwind { 507; CHECK-LABEL: test_x86_tbm_blcmsk_u32_z: 508; CHECK: # %bb.0: 509; CHECK-NEXT: blcmskl %edi, %eax 510; CHECK-NEXT: cmovel %esi, %eax 511; CHECK-NEXT: retq 512 %t0 = add i32 %a, 1 513 %t1 = xor i32 %t0, %a 514 %t2 = icmp eq i32 %t1, 0 515 %t3 = select i1 %t2, i32 %b, i32 %t1 516 ret i32 %t3 517} 518 519define i32 @test_x86_tbm_blcmsk_u32_z2(i32 %a, i32 %b, i32 %c) nounwind { 520; CHECK-LABEL: test_x86_tbm_blcmsk_u32_z2: 521; CHECK: # %bb.0: 522; CHECK-NEXT: movl %esi, %eax 523; CHECK-NEXT: blcmskl %edi, %ecx 524; CHECK-NEXT: cmovnel %edx, %eax 525; CHECK-NEXT: retq 526 %t0 = add i32 %a, 1 527 %t1 = xor i32 %t0, %a 528 %t2 = icmp eq i32 %t1, 0 529 %t3 = select i1 %t2, i32 %b, i32 %c 530 ret i32 %t3 531} 532 533define i32 @test_x86_tbm_blcmsk_u32_sle(i32 %a, i32 %b, i32 %c) nounwind { 534; CHECK-LABEL: test_x86_tbm_blcmsk_u32_sle: 535; CHECK: # %bb.0: 536; CHECK-NEXT: movl %esi, %eax 537; CHECK-NEXT: blcmskl %edi, %ecx 538; CHECK-NEXT: cmovgl %edx, %eax 539; CHECK-NEXT: retq 540 %t0 = add i32 %a, 1 541 %t1 = xor i32 %t0, %a 542 %t2 = icmp sle i32 %t1, 0 543 %t3 = select i1 %t2, i32 %b, i32 %c 544 ret i32 %t3 545} 546 547define i64 @test_x86_tbm_blcmsk_u64(i64 %a) nounwind { 548; CHECK-LABEL: test_x86_tbm_blcmsk_u64: 549; CHECK: # %bb.0: 550; CHECK-NEXT: blcmskq %rdi, %rax 551; CHECK-NEXT: retq 552 %t0 = add i64 %a, 1 553 %t1 = xor i64 %t0, %a 554 ret i64 %t1 555} 556 557define i64 @test_x86_tbm_blcmsk_u64_z(i64 %a, i64 %b) nounwind { 558; CHECK-LABEL: test_x86_tbm_blcmsk_u64_z: 559; CHECK: # %bb.0: 560; CHECK-NEXT: blcmskq %rdi, %rax 561; CHECK-NEXT: cmoveq %rsi, %rax 562; CHECK-NEXT: retq 563 %t0 = add i64 %a, 1 564 %t1 = xor i64 %t0, %a 565 %t2 = icmp eq i64 %t1, 0 566 %t3 = select i1 %t2, i64 %b, i64 %t1 567 ret i64 %t3 568} 569 570define i64 @test_x86_tbm_blcmsk_u64_z2(i64 %a, i64 %b, i64 %c) nounwind { 571; CHECK-LABEL: test_x86_tbm_blcmsk_u64_z2: 572; CHECK: # %bb.0: 573; CHECK-NEXT: movq %rsi, %rax 574; CHECK-NEXT: blcmskq %rdi, %rcx 575; CHECK-NEXT: cmovneq %rdx, %rax 576; CHECK-NEXT: retq 577 %t0 = add i64 %a, 1 578 %t1 = xor i64 %t0, %a 579 %t2 = icmp eq i64 %t1, 0 580 %t3 = select i1 %t2, i64 %b, i64 %c 581 ret i64 %t3 582} 583 584define i64 @test_x86_tbm_blcmsk_u64_sle(i64 %a, i64 %b, i64 %c) nounwind { 585; CHECK-LABEL: test_x86_tbm_blcmsk_u64_sle: 586; CHECK: # %bb.0: 587; CHECK-NEXT: movq %rsi, %rax 588; CHECK-NEXT: blcmskq %rdi, %rcx 589; CHECK-NEXT: cmovgq %rdx, %rax 590; CHECK-NEXT: retq 591 %t0 = add i64 %a, 1 592 %t1 = xor i64 %t0, %a 593 %t2 = icmp sle i64 %t1, 0 594 %t3 = select i1 %t2, i64 %b, i64 %c 595 ret i64 %t3 596} 597 598define i32 @test_x86_tbm_blcs_u32(i32 %a) nounwind { 599; CHECK-LABEL: test_x86_tbm_blcs_u32: 600; CHECK: # %bb.0: 601; CHECK-NEXT: blcsl %edi, %eax 602; CHECK-NEXT: retq 603 %t0 = add i32 %a, 1 604 %t1 = or i32 %t0, %a 605 ret i32 %t1 606} 607 608define i32 @test_x86_tbm_blcs_u32_z(i32 %a, i32 %b) nounwind { 609; CHECK-LABEL: test_x86_tbm_blcs_u32_z: 610; CHECK: # %bb.0: 611; CHECK-NEXT: blcsl %edi, %eax 612; CHECK-NEXT: cmovel %esi, %eax 613; CHECK-NEXT: retq 614 %t0 = add i32 %a, 1 615 %t1 = or i32 %t0, %a 616 %t2 = icmp eq i32 %t1, 0 617 %t3 = select i1 %t2, i32 %b, i32 %t1 618 ret i32 %t3 619} 620 621define i32 @test_x86_tbm_blcs_u32_z2(i32 %a, i32 %b, i32 %c) nounwind { 622; CHECK-LABEL: test_x86_tbm_blcs_u32_z2: 623; CHECK: # %bb.0: 624; CHECK-NEXT: movl %esi, %eax 625; CHECK-NEXT: blcsl %edi, %ecx 626; CHECK-NEXT: cmovnel %edx, %eax 627; CHECK-NEXT: retq 628 %t0 = add i32 %a, 1 629 %t1 = or i32 %t0, %a 630 %t2 = icmp eq i32 %t1, 0 631 %t3 = select i1 %t2, i32 %b, i32 %c 632 ret i32 %t3 633} 634 635define i32 @test_x86_tbm_blcs_u32_sle(i32 %a, i32 %b, i32 %c) nounwind { 636; CHECK-LABEL: test_x86_tbm_blcs_u32_sle: 637; CHECK: # %bb.0: 638; CHECK-NEXT: movl %esi, %eax 639; CHECK-NEXT: blcsl %edi, %ecx 640; CHECK-NEXT: cmovgl %edx, %eax 641; CHECK-NEXT: retq 642 %t0 = add i32 %a, 1 643 %t1 = or i32 %t0, %a 644 %t2 = icmp sle i32 %t1, 0 645 %t3 = select i1 %t2, i32 %b, i32 %c 646 ret i32 %t3 647} 648 649define i64 @test_x86_tbm_blcs_u64(i64 %a) nounwind { 650; CHECK-LABEL: test_x86_tbm_blcs_u64: 651; CHECK: # %bb.0: 652; CHECK-NEXT: blcsq %rdi, %rax 653; CHECK-NEXT: retq 654 %t0 = add i64 %a, 1 655 %t1 = or i64 %t0, %a 656 ret i64 %t1 657} 658 659define i64 @test_x86_tbm_blcs_u64_z(i64 %a, i64 %b) nounwind { 660; CHECK-LABEL: test_x86_tbm_blcs_u64_z: 661; CHECK: # %bb.0: 662; CHECK-NEXT: blcsq %rdi, %rax 663; CHECK-NEXT: cmoveq %rsi, %rax 664; CHECK-NEXT: retq 665 %t0 = add i64 %a, 1 666 %t1 = or i64 %t0, %a 667 %t2 = icmp eq i64 %t1, 0 668 %t3 = select i1 %t2, i64 %b, i64 %t1 669 ret i64 %t3 670} 671 672define i64 @test_x86_tbm_blcs_u64_z2(i64 %a, i64 %b, i64 %c) nounwind { 673; CHECK-LABEL: test_x86_tbm_blcs_u64_z2: 674; CHECK: # %bb.0: 675; CHECK-NEXT: movq %rsi, %rax 676; CHECK-NEXT: blcsq %rdi, %rcx 677; CHECK-NEXT: cmovneq %rdx, %rax 678; CHECK-NEXT: retq 679 %t0 = add i64 %a, 1 680 %t1 = or i64 %t0, %a 681 %t2 = icmp eq i64 %t1, 0 682 %t3 = select i1 %t2, i64 %b, i64 %c 683 ret i64 %t3 684} 685 686define i64 @test_x86_tbm_blcs_u64_sle(i64 %a, i64 %b, i64 %c) nounwind { 687; CHECK-LABEL: test_x86_tbm_blcs_u64_sle: 688; CHECK: # %bb.0: 689; CHECK-NEXT: movq %rsi, %rax 690; CHECK-NEXT: blcsq %rdi, %rcx 691; CHECK-NEXT: cmovgq %rdx, %rax 692; CHECK-NEXT: retq 693 %t0 = add i64 %a, 1 694 %t1 = or i64 %t0, %a 695 %t2 = icmp sle i64 %t1, 0 696 %t3 = select i1 %t2, i64 %b, i64 %c 697 ret i64 %t3 698} 699 700define i32 @test_x86_tbm_blsfill_u32(i32 %a) nounwind { 701; CHECK-LABEL: test_x86_tbm_blsfill_u32: 702; CHECK: # %bb.0: 703; CHECK-NEXT: blsfilll %edi, %eax 704; CHECK-NEXT: retq 705 %t0 = add i32 %a, -1 706 %t1 = or i32 %t0, %a 707 ret i32 %t1 708} 709 710define i32 @test_x86_tbm_blsfill_u32_z(i32 %a, i32 %b) nounwind { 711; CHECK-LABEL: test_x86_tbm_blsfill_u32_z: 712; CHECK: # %bb.0: 713; CHECK-NEXT: blsfilll %edi, %eax 714; CHECK-NEXT: cmovel %esi, %eax 715; CHECK-NEXT: retq 716 %t0 = add i32 %a, -1 717 %t1 = or i32 %t0, %a 718 %t2 = icmp eq i32 %t1, 0 719 %t3 = select i1 %t2, i32 %b, i32 %t1 720 ret i32 %t3 721} 722 723define i32 @test_x86_tbm_blsfill_u32_z2(i32 %a, i32 %b, i32 %c) nounwind { 724; CHECK-LABEL: test_x86_tbm_blsfill_u32_z2: 725; CHECK: # %bb.0: 726; CHECK-NEXT: movl %esi, %eax 727; CHECK-NEXT: blsfilll %edi, %ecx 728; CHECK-NEXT: cmovnel %edx, %eax 729; CHECK-NEXT: retq 730 %t0 = add i32 %a, -1 731 %t1 = or i32 %t0, %a 732 %t2 = icmp eq i32 %t1, 0 733 %t3 = select i1 %t2, i32 %b, i32 %c 734 ret i32 %t3 735} 736 737define i32 @test_x86_tbm_blsfill_u32_sle(i32 %a, i32 %b, i32 %c) nounwind { 738; CHECK-LABEL: test_x86_tbm_blsfill_u32_sle: 739; CHECK: # %bb.0: 740; CHECK-NEXT: movl %esi, %eax 741; CHECK-NEXT: blsfilll %edi, %ecx 742; CHECK-NEXT: cmovgl %edx, %eax 743; CHECK-NEXT: retq 744 %t0 = add i32 %a, -1 745 %t1 = or i32 %t0, %a 746 %t2 = icmp sle i32 %t1, 0 747 %t3 = select i1 %t2, i32 %b, i32 %c 748 ret i32 %t3 749} 750 751define i64 @test_x86_tbm_blsfill_u64(i64 %a) nounwind { 752; CHECK-LABEL: test_x86_tbm_blsfill_u64: 753; CHECK: # %bb.0: 754; CHECK-NEXT: blsfillq %rdi, %rax 755; CHECK-NEXT: retq 756 %t0 = add i64 %a, -1 757 %t1 = or i64 %t0, %a 758 ret i64 %t1 759} 760 761define i64 @test_x86_tbm_blsfill_u64_z(i64 %a, i64 %b) nounwind { 762; CHECK-LABEL: test_x86_tbm_blsfill_u64_z: 763; CHECK: # %bb.0: 764; CHECK-NEXT: blsfillq %rdi, %rax 765; CHECK-NEXT: cmoveq %rsi, %rax 766; CHECK-NEXT: retq 767 %t0 = add i64 %a, -1 768 %t1 = or i64 %t0, %a 769 %t2 = icmp eq i64 %t1, 0 770 %t3 = select i1 %t2, i64 %b, i64 %t1 771 ret i64 %t3 772} 773 774define i64 @test_x86_tbm_blsfill_u64_z2(i64 %a, i64 %b, i64 %c) nounwind { 775; CHECK-LABEL: test_x86_tbm_blsfill_u64_z2: 776; CHECK: # %bb.0: 777; CHECK-NEXT: movq %rsi, %rax 778; CHECK-NEXT: blsfillq %rdi, %rcx 779; CHECK-NEXT: cmovneq %rdx, %rax 780; CHECK-NEXT: retq 781 %t0 = add i64 %a, -1 782 %t1 = or i64 %t0, %a 783 %t2 = icmp eq i64 %t1, 0 784 %t3 = select i1 %t2, i64 %b, i64 %c 785 ret i64 %t3 786} 787 788define i64 @test_x86_tbm_blsfill_u64_sle(i64 %a, i64 %b, i64 %c) nounwind { 789; CHECK-LABEL: test_x86_tbm_blsfill_u64_sle: 790; CHECK: # %bb.0: 791; CHECK-NEXT: movq %rsi, %rax 792; CHECK-NEXT: blsfillq %rdi, %rcx 793; CHECK-NEXT: cmovgq %rdx, %rax 794; CHECK-NEXT: retq 795 %t0 = add i64 %a, -1 796 %t1 = or i64 %t0, %a 797 %t2 = icmp sle i64 %t1, 0 798 %t3 = select i1 %t2, i64 %b, i64 %c 799 ret i64 %t3 800} 801 802define i32 @test_x86_tbm_blsic_u32(i32 %a) nounwind { 803; CHECK-LABEL: test_x86_tbm_blsic_u32: 804; CHECK: # %bb.0: 805; CHECK-NEXT: blsicl %edi, %eax 806; CHECK-NEXT: retq 807 %t0 = xor i32 %a, -1 808 %t1 = add i32 %a, -1 809 %t2 = or i32 %t0, %t1 810 ret i32 %t2 811} 812 813define i32 @test_x86_tbm_blsic_u32_z(i32 %a, i32 %b) nounwind { 814; CHECK-LABEL: test_x86_tbm_blsic_u32_z: 815; CHECK: # %bb.0: 816; CHECK-NEXT: blsicl %edi, %eax 817; CHECK-NEXT: cmovel %esi, %eax 818; CHECK-NEXT: retq 819 %t0 = xor i32 %a, -1 820 %t1 = add i32 %a, -1 821 %t2 = or i32 %t0, %t1 822 %t3 = icmp eq i32 %t2, 0 823 %t4 = select i1 %t3, i32 %b, i32 %t2 824 ret i32 %t4 825} 826 827define i32 @test_x86_tbm_blsic_u32_z2(i32 %a, i32 %b, i32 %c) nounwind { 828; CHECK-LABEL: test_x86_tbm_blsic_u32_z2: 829; CHECK: # %bb.0: 830; CHECK-NEXT: movl %esi, %eax 831; CHECK-NEXT: blsicl %edi, %ecx 832; CHECK-NEXT: cmovnel %edx, %eax 833; CHECK-NEXT: retq 834 %t0 = xor i32 %a, -1 835 %t1 = add i32 %a, -1 836 %t2 = or i32 %t0, %t1 837 %t3 = icmp eq i32 %t2, 0 838 %t4 = select i1 %t3, i32 %b, i32 %c 839 ret i32 %t4 840} 841 842define i32 @test_x86_tbm_blsic_u32_sle(i32 %a, i32 %b, i32 %c) nounwind { 843; CHECK-LABEL: test_x86_tbm_blsic_u32_sle: 844; CHECK: # %bb.0: 845; CHECK-NEXT: movl %esi, %eax 846; CHECK-NEXT: blsicl %edi, %ecx 847; CHECK-NEXT: cmovgl %edx, %eax 848; CHECK-NEXT: retq 849 %t0 = xor i32 %a, -1 850 %t1 = add i32 %a, -1 851 %t2 = or i32 %t0, %t1 852 %t3 = icmp sle i32 %t2, 0 853 %t4 = select i1 %t3, i32 %b, i32 %c 854 ret i32 %t4 855} 856 857define i64 @test_x86_tbm_blsic_u64(i64 %a) nounwind { 858; CHECK-LABEL: test_x86_tbm_blsic_u64: 859; CHECK: # %bb.0: 860; CHECK-NEXT: blsicq %rdi, %rax 861; CHECK-NEXT: retq 862 %t0 = xor i64 %a, -1 863 %t1 = add i64 %a, -1 864 %t2 = or i64 %t0, %t1 865 ret i64 %t2 866} 867 868define i64 @test_x86_tbm_blsic_u64_z(i64 %a, i64 %b) nounwind { 869; CHECK-LABEL: test_x86_tbm_blsic_u64_z: 870; CHECK: # %bb.0: 871; CHECK-NEXT: blsicq %rdi, %rax 872; CHECK-NEXT: cmoveq %rsi, %rax 873; CHECK-NEXT: retq 874 %t0 = xor i64 %a, -1 875 %t1 = add i64 %a, -1 876 %t2 = or i64 %t0, %t1 877 %t3 = icmp eq i64 %t2, 0 878 %t4 = select i1 %t3, i64 %b, i64 %t2 879 ret i64 %t4 880} 881 882define i64 @test_x86_tbm_blsic_u64_z2(i64 %a, i64 %b, i64 %c) nounwind { 883; CHECK-LABEL: test_x86_tbm_blsic_u64_z2: 884; CHECK: # %bb.0: 885; CHECK-NEXT: movq %rsi, %rax 886; CHECK-NEXT: blsicq %rdi, %rcx 887; CHECK-NEXT: cmovneq %rdx, %rax 888; CHECK-NEXT: retq 889 %t0 = xor i64 %a, -1 890 %t1 = add i64 %a, -1 891 %t2 = or i64 %t0, %t1 892 %t3 = icmp eq i64 %t2, 0 893 %t4 = select i1 %t3, i64 %b, i64 %c 894 ret i64 %t4 895} 896 897define i64 @test_x86_tbm_blsic_u64_sle(i64 %a, i64 %b, i64 %c) nounwind { 898; CHECK-LABEL: test_x86_tbm_blsic_u64_sle: 899; CHECK: # %bb.0: 900; CHECK-NEXT: movq %rsi, %rax 901; CHECK-NEXT: blsicq %rdi, %rcx 902; CHECK-NEXT: cmovgq %rdx, %rax 903; CHECK-NEXT: retq 904 %t0 = xor i64 %a, -1 905 %t1 = add i64 %a, -1 906 %t2 = or i64 %t0, %t1 907 %t3 = icmp sle i64 %t2, 0 908 %t4 = select i1 %t3, i64 %b, i64 %c 909 ret i64 %t4 910} 911 912define i32 @test_x86_tbm_t1mskc_u32(i32 %a) nounwind { 913; CHECK-LABEL: test_x86_tbm_t1mskc_u32: 914; CHECK: # %bb.0: 915; CHECK-NEXT: t1mskcl %edi, %eax 916; CHECK-NEXT: retq 917 %t0 = xor i32 %a, -1 918 %t1 = add i32 %a, 1 919 %t2 = or i32 %t0, %t1 920 ret i32 %t2 921} 922 923define i32 @test_x86_tbm_t1mskc_u32_z(i32 %a, i32 %b) nounwind { 924; CHECK-LABEL: test_x86_tbm_t1mskc_u32_z: 925; CHECK: # %bb.0: 926; CHECK-NEXT: t1mskcl %edi, %eax 927; CHECK-NEXT: cmovel %esi, %eax 928; CHECK-NEXT: retq 929 %t0 = xor i32 %a, -1 930 %t1 = add i32 %a, 1 931 %t2 = or i32 %t0, %t1 932 %t3 = icmp eq i32 %t2, 0 933 %t4 = select i1 %t3, i32 %b, i32 %t2 934 ret i32 %t4 935} 936 937define i32 @test_x86_tbm_t1mskc_u32_z2(i32 %a, i32 %b, i32 %c) nounwind { 938; CHECK-LABEL: test_x86_tbm_t1mskc_u32_z2: 939; CHECK: # %bb.0: 940; CHECK-NEXT: movl %esi, %eax 941; CHECK-NEXT: t1mskcl %edi, %ecx 942; CHECK-NEXT: cmovnel %edx, %eax 943; CHECK-NEXT: retq 944 %t0 = xor i32 %a, -1 945 %t1 = add i32 %a, 1 946 %t2 = or i32 %t0, %t1 947 %t3 = icmp eq i32 %t2, 0 948 %t4 = select i1 %t3, i32 %b, i32 %c 949 ret i32 %t4 950} 951 952define i32 @test_x86_tbm_t1mskc_u32_sle(i32 %a, i32 %b, i32 %c) nounwind { 953; CHECK-LABEL: test_x86_tbm_t1mskc_u32_sle: 954; CHECK: # %bb.0: 955; CHECK-NEXT: movl %esi, %eax 956; CHECK-NEXT: t1mskcl %edi, %ecx 957; CHECK-NEXT: cmovgl %edx, %eax 958; CHECK-NEXT: retq 959 %t0 = xor i32 %a, -1 960 %t1 = add i32 %a, 1 961 %t2 = or i32 %t0, %t1 962 %t3 = icmp sle i32 %t2, 0 963 %t4 = select i1 %t3, i32 %b, i32 %c 964 ret i32 %t4 965} 966 967define i64 @test_x86_tbm_t1mskc_u64(i64 %a) nounwind { 968; CHECK-LABEL: test_x86_tbm_t1mskc_u64: 969; CHECK: # %bb.0: 970; CHECK-NEXT: t1mskcq %rdi, %rax 971; CHECK-NEXT: retq 972 %t0 = xor i64 %a, -1 973 %t1 = add i64 %a, 1 974 %t2 = or i64 %t0, %t1 975 ret i64 %t2 976} 977 978define i64 @test_x86_tbm_t1mskc_u64_z(i64 %a, i64 %b) nounwind { 979; CHECK-LABEL: test_x86_tbm_t1mskc_u64_z: 980; CHECK: # %bb.0: 981; CHECK-NEXT: t1mskcq %rdi, %rax 982; CHECK-NEXT: cmoveq %rsi, %rax 983; CHECK-NEXT: retq 984 %t0 = xor i64 %a, -1 985 %t1 = add i64 %a, 1 986 %t2 = or i64 %t0, %t1 987 %t3 = icmp eq i64 %t2, 0 988 %t4 = select i1 %t3, i64 %b, i64 %t2 989 ret i64 %t4 990} 991 992define i64 @test_x86_tbm_t1mskc_u64_z2(i64 %a, i64 %b, i64 %c) nounwind { 993; CHECK-LABEL: test_x86_tbm_t1mskc_u64_z2: 994; CHECK: # %bb.0: 995; CHECK-NEXT: movq %rsi, %rax 996; CHECK-NEXT: t1mskcq %rdi, %rcx 997; CHECK-NEXT: cmovneq %rdx, %rax 998; CHECK-NEXT: retq 999 %t0 = xor i64 %a, -1 1000 %t1 = add i64 %a, 1 1001 %t2 = or i64 %t0, %t1 1002 %t3 = icmp eq i64 %t2, 0 1003 %t4 = select i1 %t3, i64 %b, i64 %c 1004 ret i64 %t4 1005} 1006 1007define i64 @test_x86_tbm_t1mskc_u64_sle(i64 %a, i64 %b, i64 %c) nounwind { 1008; CHECK-LABEL: test_x86_tbm_t1mskc_u64_sle: 1009; CHECK: # %bb.0: 1010; CHECK-NEXT: movq %rsi, %rax 1011; CHECK-NEXT: t1mskcq %rdi, %rcx 1012; CHECK-NEXT: cmovgq %rdx, %rax 1013; CHECK-NEXT: retq 1014 %t0 = xor i64 %a, -1 1015 %t1 = add i64 %a, 1 1016 %t2 = or i64 %t0, %t1 1017 %t3 = icmp sle i64 %t2, 0 1018 %t4 = select i1 %t3, i64 %b, i64 %c 1019 ret i64 %t4 1020} 1021 1022define i32 @test_x86_tbm_tzmsk_u32(i32 %a) nounwind { 1023; CHECK-LABEL: test_x86_tbm_tzmsk_u32: 1024; CHECK: # %bb.0: 1025; CHECK-NEXT: tzmskl %edi, %eax 1026; CHECK-NEXT: retq 1027 %t0 = xor i32 %a, -1 1028 %t1 = add i32 %a, -1 1029 %t2 = and i32 %t0, %t1 1030 ret i32 %t2 1031} 1032 1033define i32 @test_x86_tbm_tzmsk_u32_z(i32 %a, i32 %b) nounwind { 1034; CHECK-LABEL: test_x86_tbm_tzmsk_u32_z: 1035; CHECK: # %bb.0: 1036; CHECK-NEXT: tzmskl %edi, %eax 1037; CHECK-NEXT: cmovel %esi, %eax 1038; CHECK-NEXT: retq 1039 %t0 = xor i32 %a, -1 1040 %t1 = add i32 %a, -1 1041 %t2 = and i32 %t0, %t1 1042 %t3 = icmp eq i32 %t2, 0 1043 %t4 = select i1 %t3, i32 %b, i32 %t2 1044 ret i32 %t4 1045} 1046 1047define i32 @test_x86_tbm_tzmsk_u32_z2(i32 %a, i32 %b, i32 %c) nounwind { 1048; CHECK-LABEL: test_x86_tbm_tzmsk_u32_z2: 1049; CHECK: # %bb.0: 1050; CHECK-NEXT: movl %esi, %eax 1051; CHECK-NEXT: tzmskl %edi, %ecx 1052; CHECK-NEXT: cmovnel %edx, %eax 1053; CHECK-NEXT: retq 1054 %t0 = xor i32 %a, -1 1055 %t1 = add i32 %a, -1 1056 %t2 = and i32 %t0, %t1 1057 %t3 = icmp eq i32 %t2, 0 1058 %t4 = select i1 %t3, i32 %b, i32 %c 1059 ret i32 %t4 1060} 1061 1062define i32 @test_x86_tbm_tzmsk_u32_sle(i32 %a, i32 %b, i32 %c) nounwind { 1063; CHECK-LABEL: test_x86_tbm_tzmsk_u32_sle: 1064; CHECK: # %bb.0: 1065; CHECK-NEXT: movl %esi, %eax 1066; CHECK-NEXT: tzmskl %edi, %ecx 1067; CHECK-NEXT: cmovgl %edx, %eax 1068; CHECK-NEXT: retq 1069 %t0 = xor i32 %a, -1 1070 %t1 = add i32 %a, -1 1071 %t2 = and i32 %t0, %t1 1072 %t3 = icmp sle i32 %t2, 0 1073 %t4 = select i1 %t3, i32 %b, i32 %c 1074 ret i32 %t4 1075} 1076 1077define i64 @test_x86_tbm_tzmsk_u64(i64 %a) nounwind { 1078; CHECK-LABEL: test_x86_tbm_tzmsk_u64: 1079; CHECK: # %bb.0: 1080; CHECK-NEXT: tzmskq %rdi, %rax 1081; CHECK-NEXT: retq 1082 %t0 = xor i64 %a, -1 1083 %t1 = add i64 %a, -1 1084 %t2 = and i64 %t0, %t1 1085 ret i64 %t2 1086} 1087 1088define i64 @test_x86_tbm_tzmsk_u64_z(i64 %a, i64 %b) nounwind { 1089; CHECK-LABEL: test_x86_tbm_tzmsk_u64_z: 1090; CHECK: # %bb.0: 1091; CHECK-NEXT: tzmskq %rdi, %rax 1092; CHECK-NEXT: cmoveq %rsi, %rax 1093; CHECK-NEXT: retq 1094 %t0 = xor i64 %a, -1 1095 %t1 = add i64 %a, -1 1096 %t2 = and i64 %t0, %t1 1097 %t3 = icmp eq i64 %t2, 0 1098 %t4 = select i1 %t3, i64 %b, i64 %t2 1099 ret i64 %t4 1100} 1101 1102define i64 @test_x86_tbm_tzmsk_u64_z2(i64 %a, i64 %b, i64 %c) nounwind { 1103; CHECK-LABEL: test_x86_tbm_tzmsk_u64_z2: 1104; CHECK: # %bb.0: 1105; CHECK-NEXT: movq %rsi, %rax 1106; CHECK-NEXT: tzmskq %rdi, %rcx 1107; CHECK-NEXT: cmovneq %rdx, %rax 1108; CHECK-NEXT: retq 1109 %t0 = xor i64 %a, -1 1110 %t1 = add i64 %a, -1 1111 %t2 = and i64 %t0, %t1 1112 %t3 = icmp eq i64 %t2, 0 1113 %t4 = select i1 %t3, i64 %b, i64 %c 1114 ret i64 %t4 1115} 1116 1117define i64 @test_x86_tbm_tzmsk_u64_sle(i64 %a, i64 %b, i64 %c) nounwind { 1118; CHECK-LABEL: test_x86_tbm_tzmsk_u64_sle: 1119; CHECK: # %bb.0: 1120; CHECK-NEXT: movq %rsi, %rax 1121; CHECK-NEXT: tzmskq %rdi, %rcx 1122; CHECK-NEXT: cmovgq %rdx, %rax 1123; CHECK-NEXT: retq 1124 %t0 = xor i64 %a, -1 1125 %t1 = add i64 %a, -1 1126 %t2 = and i64 %t0, %t1 1127 %t3 = icmp sle i64 %t2, 0 1128 %t4 = select i1 %t3, i64 %b, i64 %c 1129 ret i64 %t4 1130} 1131 1132define i64 @test_and_large_constant_mask(i64 %x) { 1133; CHECK-LABEL: test_and_large_constant_mask: 1134; CHECK: # %bb.0: # %entry 1135; CHECK-NEXT: bextrq $15872, %rdi, %rax # imm = 0x3E00 1136; CHECK-NEXT: retq 1137entry: 1138 %and = and i64 %x, 4611686018427387903 1139 ret i64 %and 1140} 1141 1142define i64 @test_and_large_constant_mask_load(ptr %x) { 1143; CHECK-LABEL: test_and_large_constant_mask_load: 1144; CHECK: # %bb.0: # %entry 1145; CHECK-NEXT: bextrq $15872, (%rdi), %rax # imm = 0x3E00 1146; CHECK-NEXT: retq 1147entry: 1148 %x1 = load i64, ptr %x 1149 %and = and i64 %x1, 4611686018427387903 1150 ret i64 %and 1151} 1152 1153; Make sure the mask doesn't break our matching of blcic 1154define i64 @masked_blcic(i64) { 1155; CHECK-LABEL: masked_blcic: 1156; CHECK: # %bb.0: 1157; CHECK-NEXT: movzwl %di, %eax 1158; CHECK-NEXT: blcicl %eax, %eax 1159; CHECK-NEXT: retq 1160 %2 = and i64 %0, 65535 1161 %3 = xor i64 %2, -1 1162 %4 = add nuw nsw i64 %2, 1 1163 %5 = and i64 %4, %3 1164 ret i64 %5 1165} 1166 1167define i32 @blcic32_branch(i32 %x) nounwind { 1168; CHECK-LABEL: blcic32_branch: 1169; CHECK: # %bb.0: 1170; CHECK-NEXT: pushq %rbx 1171; CHECK-NEXT: blcicl %edi, %ebx 1172; CHECK-NEXT: jne .LBB89_2 1173; CHECK-NEXT: # %bb.1: 1174; CHECK-NEXT: callq bar@PLT 1175; CHECK-NEXT: .LBB89_2: 1176; CHECK-NEXT: movl %ebx, %eax 1177; CHECK-NEXT: popq %rbx 1178; CHECK-NEXT: retq 1179 %tmp = xor i32 %x, -1 1180 %tmp2 = add i32 %x, 1 1181 %tmp3 = and i32 %tmp, %tmp2 1182 %cmp = icmp eq i32 %tmp3, 0 1183 br i1 %cmp, label %1, label %2 1184 1185 tail call void @bar() 1186 br label %2 1187 ret i32 %tmp3 1188} 1189 1190define i64 @blcic64_branch(i64 %x) nounwind { 1191; CHECK-LABEL: blcic64_branch: 1192; CHECK: # %bb.0: 1193; CHECK-NEXT: pushq %rbx 1194; CHECK-NEXT: blcicq %rdi, %rbx 1195; CHECK-NEXT: jne .LBB90_2 1196; CHECK-NEXT: # %bb.1: 1197; CHECK-NEXT: callq bar@PLT 1198; CHECK-NEXT: .LBB90_2: 1199; CHECK-NEXT: movq %rbx, %rax 1200; CHECK-NEXT: popq %rbx 1201; CHECK-NEXT: retq 1202 %tmp = xor i64 %x, -1 1203 %tmp2 = add i64 %x, 1 1204 %tmp3 = and i64 %tmp, %tmp2 1205 %cmp = icmp eq i64 %tmp3, 0 1206 br i1 %cmp, label %1, label %2 1207 1208 tail call void @bar() 1209 br label %2 1210 ret i64 %tmp3 1211} 1212 1213define i32 @tzmsk32_branch(i32 %x) nounwind { 1214; CHECK-LABEL: tzmsk32_branch: 1215; CHECK: # %bb.0: 1216; CHECK-NEXT: pushq %rbx 1217; CHECK-NEXT: tzmskl %edi, %ebx 1218; CHECK-NEXT: jne .LBB91_2 1219; CHECK-NEXT: # %bb.1: 1220; CHECK-NEXT: callq bar@PLT 1221; CHECK-NEXT: .LBB91_2: 1222; CHECK-NEXT: movl %ebx, %eax 1223; CHECK-NEXT: popq %rbx 1224; CHECK-NEXT: retq 1225 %tmp = xor i32 %x, -1 1226 %tmp2 = add i32 %x, -1 1227 %tmp3 = and i32 %tmp, %tmp2 1228 %cmp = icmp eq i32 %tmp3, 0 1229 br i1 %cmp, label %1, label %2 1230 1231 tail call void @bar() 1232 br label %2 1233 ret i32 %tmp3 1234} 1235 1236define i64 @tzmsk64_branch(i64 %x) nounwind { 1237; CHECK-LABEL: tzmsk64_branch: 1238; CHECK: # %bb.0: 1239; CHECK-NEXT: pushq %rbx 1240; CHECK-NEXT: tzmskq %rdi, %rbx 1241; CHECK-NEXT: jne .LBB92_2 1242; CHECK-NEXT: # %bb.1: 1243; CHECK-NEXT: callq bar@PLT 1244; CHECK-NEXT: .LBB92_2: 1245; CHECK-NEXT: movq %rbx, %rax 1246; CHECK-NEXT: popq %rbx 1247; CHECK-NEXT: retq 1248 %tmp = xor i64 %x, -1 1249 %tmp2 = add i64 %x, -1 1250 %tmp3 = and i64 %tmp, %tmp2 1251 %cmp = icmp eq i64 %tmp3, 0 1252 br i1 %cmp, label %1, label %2 1253 1254 tail call void @bar() 1255 br label %2 1256 ret i64 %tmp3 1257} 1258 1259define i32 @blcfill32_branch(i32 %x) nounwind { 1260; CHECK-LABEL: blcfill32_branch: 1261; CHECK: # %bb.0: 1262; CHECK-NEXT: pushq %rbx 1263; CHECK-NEXT: blcfilll %edi, %ebx 1264; CHECK-NEXT: jne .LBB93_2 1265; CHECK-NEXT: # %bb.1: 1266; CHECK-NEXT: callq bar@PLT 1267; CHECK-NEXT: .LBB93_2: 1268; CHECK-NEXT: movl %ebx, %eax 1269; CHECK-NEXT: popq %rbx 1270; CHECK-NEXT: retq 1271 %tmp2 = add i32 %x, 1 1272 %tmp3 = and i32 %tmp2, %x 1273 %cmp = icmp eq i32 %tmp3, 0 1274 br i1 %cmp, label %1, label %2 1275 1276 tail call void @bar() 1277 br label %2 1278 ret i32 %tmp3 1279} 1280 1281define i64 @blcfill64_branch(i64 %x) nounwind { 1282; CHECK-LABEL: blcfill64_branch: 1283; CHECK: # %bb.0: 1284; CHECK-NEXT: pushq %rbx 1285; CHECK-NEXT: blcfillq %rdi, %rbx 1286; CHECK-NEXT: jne .LBB94_2 1287; CHECK-NEXT: # %bb.1: 1288; CHECK-NEXT: callq bar@PLT 1289; CHECK-NEXT: .LBB94_2: 1290; CHECK-NEXT: movq %rbx, %rax 1291; CHECK-NEXT: popq %rbx 1292; CHECK-NEXT: retq 1293 %tmp2 = add i64 %x, 1 1294 %tmp3 = and i64 %tmp2, %x 1295 %cmp = icmp eq i64 %tmp3, 0 1296 br i1 %cmp, label %1, label %2 1297 1298 tail call void @bar() 1299 br label %2 1300 ret i64 %tmp3 1301} 1302 1303declare void @bar() 1304