xref: /llvm-project/llvm/test/CodeGen/X86/tail-call-conditional.mir (revision c81a121f3f230cfe468b6def6d2904b4aefb855b)
1# RUN: llc -mtriple x86_64-- -verify-machineinstrs -run-pass branch-folder -o - %s | FileCheck %s
2
3# Check the TCRETURNdi64cc optimization.
4
5--- |
6  target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
7
8  define i64 @test(i64 %arg, ptr %arg1) optsize {
9    %tmp = icmp ult i64 %arg, 100
10    br i1 %tmp, label %1, label %4
11
12    %tmp3 = icmp ult i64 %arg, 10
13    br i1 %tmp3, label %2, label %3
14
15    %tmp5 = tail call i64 @f1(ptr %arg1, i64 %arg)
16    ret i64 %tmp5
17
18    %tmp7 = tail call i64 @f2(ptr %arg1, i64 %arg)
19    ret i64 %tmp7
20
21    ret i64 123
22  }
23
24  declare i64 @f1(ptr, i64)
25  declare i64 @f2(ptr, i64)
26
27...
28---
29name: test
30tracksRegLiveness: true
31liveins:
32  - { reg: '$rdi' }
33  - { reg: '$rsi' }
34body:             |
35  bb.0:
36    successors: %bb.1, %bb.4
37    liveins: $rdi, $rsi
38
39    $rax = COPY $rdi
40    CMP64ri32 $rax, 99, implicit-def $eflags
41    JCC_1 %bb.4, 7, implicit $eflags
42    JMP_1 %bb.1
43
44  ; CHECK: bb.1:
45  ; CHECK-NEXT: successors: %bb.2({{[^)]+}}){{$}}
46  ; CHECK-NEXT: liveins: $rax, $rsi
47  ; CHECK-NEXT: {{^  $}}
48  ; CHECK-NEXT: $rdi = COPY $rsi
49  ; CHECK-NEXT: $rsi = COPY $rax
50  ; CHECK-NEXT: CMP64ri32 $rax, 9, implicit-def $eflags
51  ; CHECK-NEXT: TCRETURNdi64cc @f1, 0, 6, csr_64, implicit $rsp, implicit $eflags, implicit $ssp, implicit $rsp, implicit $rdi, implicit $rsi, implicit $rdi, implicit-def $rdi, implicit $hsi, implicit-def $hsi, implicit $sih, implicit-def $sih, implicit $sil, implicit-def $sil, implicit $si, implicit-def $si, implicit $esi, implicit-def $esi, implicit $rsi, implicit-def $rsi, implicit $hdi, implicit-def $hdi, implicit $dih, implicit-def $dih, implicit $dil, implicit-def $dil, implicit $di, implicit-def $di, implicit $edi, implicit-def $edi
52
53  bb.1:
54    successors: %bb.2, %bb.3
55    liveins: $rax, $rsi
56
57    CMP64ri32 $rax, 9, implicit-def $eflags
58    JCC_1 %bb.3, 7, implicit $eflags
59    JMP_1 %bb.2
60
61  bb.2:
62    liveins: $rax, $rsi
63
64    $rdi = COPY $rsi
65    $rsi = COPY $rax
66
67    TCRETURNdi64 @f1, 0, csr_64, implicit $rsp, implicit $rdi, implicit $rsi
68
69  ; CHECK: bb.2:
70  ; CHECK-NEXT: liveins: $rdi, $rsi
71  ; CHECK-NEXT: {{^  $}}
72  ; CHECK-NEXT: TCRETURNdi64 @f2, 0, csr_64, implicit $rsp, implicit $rdi, implicit $rsi
73
74  bb.3:
75    liveins: $rax, $rsi
76
77    $rdi = COPY $rsi
78    $rsi = COPY $rax
79    TCRETURNdi64 @f2, 0, csr_64, implicit $rsp, implicit $rdi, implicit $rsi
80
81  bb.4:
82    dead $eax = MOV32ri 123, implicit-def $rax
83    RET 0, $rax
84
85...
86