xref: /llvm-project/llvm/test/CodeGen/X86/subreg-to-reg-6.ll (revision 0620a637e362d1add1fe506307a25d0353e254f5)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
3
4define i64 @foo() nounwind {
5; CHECK-LABEL: foo:
6; CHECK:       # %bb.0: # %entry
7; CHECK-NEXT:    cmpl $12, 0
8; CHECK-NEXT:    je .LBB0_1
9; CHECK-NEXT:  # %bb.2: # %bb65
10; CHECK-NEXT:    xorl %ecx, %ecx
11; CHECK-NEXT:    #APP
12; CHECK-NEXT:    #NO_APP
13; CHECK-NEXT:    xorl %eax, %eax
14; CHECK-NEXT:    retq
15; CHECK-NEXT:  .LBB0_1: # %bb56
16entry:
17	%t0 = load i32, ptr null, align 8
18	switch i32 %t0, label %bb65 [
19		i32 16, label %bb
20		i32 12, label %bb56
21	]
22
23bb:
24	br label %bb65
25
26bb56:
27	unreachable
28
29bb65:
30	%a = phi i64 [ 0, %bb ], [ 0, %entry ]
31	tail call void asm "", "{cx}"(i64 %a) nounwind
32	%t15 = and i64 %a, 4294967295
33	ret i64 %t15
34}
35
36define i64 @bar(i64 %t0) nounwind {
37; CHECK-LABEL: bar:
38; CHECK:       # %bb.0:
39; CHECK-NEXT:    movq %rdi, %rax
40; CHECK-NEXT:    xorl %ecx, %ecx
41; CHECK-NEXT:    #APP
42; CHECK-NEXT:    #NO_APP
43; CHECK-NEXT:    negl %eax
44; CHECK-NEXT:    retq
45	call void asm "", "{cx}"(i64 0) nounwind
46	%t1 = sub i64 0, %t0
47	%t2 = and i64 %t1, 4294967295
48	ret i64 %t2
49}
50