xref: /llvm-project/llvm/test/CodeGen/X86/subreg-to-reg-3.ll (revision 0620a637e362d1add1fe506307a25d0353e254f5)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
3
4; Don't eliminate or coalesce away the explicit zero-extension!
5
6define i64 @foo(i64 %a) {
7; CHECK-LABEL: foo:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    imull $7823, %edi, %eax # imm = 0x1E8F
10; CHECK-NEXT:    incq %rax
11; CHECK-NEXT:    retq
12  %b = mul i64 %a, 7823
13  %c = and i64 %b, 4294967295
14  %d = add i64 %c, 1
15  ret i64 %d
16}
17