xref: /llvm-project/llvm/test/CodeGen/X86/subreg-to-reg-1.ll (revision 0620a637e362d1add1fe506307a25d0353e254f5)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
3
4; Don't eliminate or coalesce away the explicit zero-extension!
5; This is currently using an leal because of a 3-addressification detail,
6; though this isn't necessary; The point of this test is to make sure
7; a 32-bit add is used.
8
9define i64 @foo(i64 %a) nounwind {
10; CHECK-LABEL: foo:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    leal -1(%rdi), %eax
13; CHECK-NEXT:    incq %rax
14; CHECK-NEXT:    retq
15  %b = add i64 %a, 4294967295
16  %c = and i64 %b, 4294967295
17  %d = add i64 %c, 1
18  ret i64 %d
19}
20