xref: /llvm-project/llvm/test/CodeGen/X86/subreg-to-reg-0.ll (revision 2f448bf509432c1a19ec46ab8cbc7353c03c6280)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
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4; Do eliminate the zero-extension instruction and rely on
5; x86-64's implicit zero-extension!
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7define i64 @foo(ptr %p) nounwind {
8; CHECK-LABEL: foo:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    movl (%rdi), %eax
11; CHECK-NEXT:    incl %eax
12; CHECK-NEXT:    retq
13  %t = load i32, ptr %p
14  %n = add i32 %t, 1
15  %z = zext i32 %n to i64
16  ret i64 %z
17}
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