1# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2# RUN: llc -o - %s -fixup-allow-gcptr-in-csr=true -start-after=finalize-isel | FileCheck %s 3 4--- | 5 ; ModuleID = 'test/CodeGen/X86/statepoint-vreg.ll' 6 source_filename = "test/CodeGen/X86/statepoint-vreg.ll" 7 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" 8 target triple = "x86_64-pc-linux-gnu" 9 10 declare void @bar() 11 12 define i32 @test_basic(ptr addrspace(1) %obj1, ptr addrspace(1) %obj2) gc "statepoint-example" { 13 ; CHECK-LABEL: test_basic: 14 ; CHECK: # %bb.0: 15 ; CHECK-NEXT: pushq %r14 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16 17 ; CHECK-NEXT: pushq %rbx 18 ; CHECK-NEXT: .cfi_def_cfa_offset 24 19 ; CHECK-NEXT: pushq %rax 20 ; CHECK-NEXT: .cfi_def_cfa_offset 32 21 ; CHECK-NEXT: .cfi_offset %rbx, -24 22 ; CHECK-NEXT: .cfi_offset %r14, -16 23 ; CHECK-NEXT: movq %rsi, %rbx 24 ; CHECK-NEXT: movq %rdi, %r14 25 ; CHECK-NEXT: callq bar 26 ; CHECK-NEXT: .Ltmp0: 27 ; CHECK-NEXT: movl (%r14), %eax 28 ; CHECK-NEXT: addl (%rbx), %eax 29 ; CHECK-NEXT: addq $8, %rsp 30 ; CHECK-NEXT: .cfi_def_cfa_offset 24 31 ; CHECK-NEXT: popq %rbx 32 ; CHECK-NEXT: .cfi_def_cfa_offset 16 33 ; CHECK-NEXT: popq %r14 34 ; CHECK-NEXT: .cfi_def_cfa_offset 8 35 ; CHECK-NEXT: retq 36 %token = call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 2882400000, i32 0, ptr elementtype(void ()) @bar, i32 0, i32 0, i32 0, i32 0) [ "gc-live"(ptr addrspace(1) %obj1, ptr addrspace(1) %obj2) ] 37 %rel1 = call coldcc ptr addrspace(1) @llvm.experimental.gc.relocate.p1(token %token, i32 0, i32 0) ; (%obj1, %obj1) 38 %rel2 = call coldcc ptr addrspace(1) @llvm.experimental.gc.relocate.p1(token %token, i32 1, i32 1) ; (%obj2, %obj2) 39 %a = load i32, ptr addrspace(1) %rel1, align 4 40 %b = load i32, ptr addrspace(1) %rel2, align 4 41 %c = add i32 %a, %b 42 ret i32 %c 43 } 44 45 ; CHECK-LABEL: __LLVM_StackMaps: 46 ; CHECK-NEXT: .byte 3 47 ; CHECK-NEXT: .byte 0 48 ; CHECK-NEXT: .short 0 49 ; CHECK-NEXT: .long 1 50 ; CHECK-NEXT: .long 0 51 ; CHECK-NEXT: .long 1 52 ; CHECK-NEXT: .quad test_basic 53 ; CHECK-NEXT: .quad 24 54 ; CHECK-NEXT: .quad 1 55 ; CHECK-NEXT: .quad 2882400000 56 ; CHECK-NEXT: .long .Ltmp0-test_basic 57 ; CHECK-NEXT: .short 0 58 ; CHECK-NEXT: .short 8 59 ; CHECK-NEXT: .byte 4 60 ; CHECK-NEXT: .byte 0 61 ; CHECK-NEXT: .short 8 62 ; CHECK-NEXT: .short 0 63 ; CHECK-NEXT: .short 0 64 ; CHECK-NEXT: .long 0 65 ; CHECK-NEXT: .byte 4 66 ; CHECK-NEXT: .byte 0 67 ; CHECK-NEXT: .short 8 68 ; CHECK-NEXT: .short 0 69 ; CHECK-NEXT: .short 0 70 ; CHECK-NEXT: .long 0 71 ; CHECK-NEXT: .byte 4 72 ; CHECK-NEXT: .byte 0 73 ; CHECK-NEXT: .short 8 74 ; CHECK-NEXT: .short 0 75 ; CHECK-NEXT: .short 0 76 ; CHECK-NEXT: .long 1 77 ; CHECK-NEXT: .byte 4 78 ; CHECK-NEXT: .byte 0 79 ; CHECK-NEXT: .short 8 80 ; CHECK-NEXT: .short 0 81 ; CHECK-NEXT: .short 0 82 ; CHECK-NEXT: .long 0 83 ; CHECK-NEXT: .byte 1 84 ; CHECK-NEXT: .byte 0 85 ; CHECK-NEXT: .short 8 86 ; CHECK-NEXT: .short 3 87 ; CHECK-NEXT: .short 0 88 ; CHECK-NEXT: .long 0 89 ; CHECK-NEXT: .byte 1 90 ; CHECK-NEXT: .byte 0 91 ; CHECK-NEXT: .short 8 92 ; CHECK-NEXT: .short 3 93 ; CHECK-NEXT: .short 0 94 ; CHECK-NEXT: .long 0 95 ; CHECK-NEXT: .byte 1 96 ; CHECK-NEXT: .byte 0 97 ; CHECK-NEXT: .short 8 98 ; CHECK-NEXT: .short 14 99 ; CHECK-NEXT: .short 0 100 ; CHECK-NEXT: .long 0 101 ; CHECK-NEXT: .byte 1 102 ; CHECK-NEXT: .byte 0 103 ; CHECK-NEXT: .short 8 104 ; CHECK-NEXT: .short 14 105 ; CHECK-NEXT: .short 0 106 ; CHECK-NEXT: .long 0 107 ; CHECK-NEXT: .p2align 3 108 ; CHECK-NEXT: .short 0 109 ; CHECK-NEXT: .short 0 110 ; CHECK-NEXT: .p2align 3 111 112 declare token @llvm.experimental.gc.statepoint.p0(i64 immarg, i32 immarg, ptr, i32 immarg, i32 immarg, ...) 113 114 ; Function Attrs: nounwind readonly 115 declare ptr addrspace(1) @llvm.experimental.gc.relocate.p1(token, i32 immarg, i32 immarg) #0 116 117 attributes #0 = { nounwind readonly } 118 attributes #1 = { nounwind } 119 120... 121--- 122name: test_basic 123alignment: 16 124selected: false 125failedISel: false 126tracksRegLiveness: true 127registers: 128 - { id: 0, class: gr64, preferred-register: '' } 129 - { id: 1, class: gr64, preferred-register: '' } 130 - { id: 2, class: gr64, preferred-register: '' } 131 - { id: 3, class: gr64, preferred-register: '' } 132 - { id: 4, class: gr32, preferred-register: '' } 133 - { id: 5, class: gr32, preferred-register: '' } 134liveins: 135 - { reg: '$rdi', virtual-reg: '%0' } 136 - { reg: '$rsi', virtual-reg: '%1' } 137frameInfo: 138 adjustsStack: true 139fixedStack: [] 140stack: [] 141callSites: [] 142constants: [] 143machineFunctionInfo: {} 144body: | 145 bb.0 (%ir-block.0): 146 liveins: $rdi, $rsi 147 148 %1:gr64 = COPY $rsi 149 %0:gr64 = COPY $rdi 150 ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp 151 %2:gr64, %3:gr64 = STATEPOINT 2882400000, 0, 0, @bar, 2, 0, 2, 0, 2, 1, 2, 0, 2, 2, %1(tied-def 0), %0(tied-def 1), 2, 0, 2, 2, 0, 0, 1, 1, csr_64, implicit-def $rsp, implicit-def $ssp 152 ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp 153 %4:gr32 = MOV32rm killed %3, 1, $noreg, 0, $noreg :: (load (s32) from %ir.rel1, addrspace 1) 154 %5:gr32 = ADD32rm %4, killed %2, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.rel2, addrspace 1) 155 $eax = COPY %5 156 RET 0, $eax 157 158... 159