xref: /llvm-project/llvm/test/CodeGen/X86/split-extend-vector-inreg.ll (revision e6bf48d11047e970cb24554a01b65b566d6b5d22)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s
3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s
4
5define <4 x i64> @autogen_SD88863() {
6; CHECK-LABEL: autogen_SD88863:
7; CHECK:       # %bb.0: # %BB
8; CHECK-NEXT:    vperm2f128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1]
9; CHECK-NEXT:    vxorpd %xmm1, %xmm1, %xmm1
10; CHECK-NEXT:    vshufpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[3],ymm1[3]
11; CHECK-NEXT:    movb $1, %al
12; CHECK-NEXT:    .p2align 4
13; CHECK-NEXT:  .LBB0_1: # %CF
14; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
15; CHECK-NEXT:    testb %al, %al
16; CHECK-NEXT:    jne .LBB0_1
17; CHECK-NEXT:  # %bb.2: # %CF240
18; CHECK-NEXT:    ret{{[l|q]}}
19BB:
20  %I26 = insertelement <4 x i64> undef, i64 undef, i32 2
21  br label %CF
22
23CF:
24  %E66 = extractelement <4 x i64> %I26, i32 1
25  %I68 = insertelement <4 x i64> zeroinitializer, i64 %E66, i32 2
26  %Cmp72 = icmp eq i32 0, 0
27  br i1 %Cmp72, label %CF, label %CF240
28
29CF240:
30  ret <4 x i64> %I68
31}
32