xref: /llvm-project/llvm/test/CodeGen/X86/sm4-intrinsics.ll (revision 049d6a3f428efeb1a22f62e55b808f60b0bf27cc) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sm4 | FileCheck %s
3; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sm4 | FileCheck %s
4
5define <4 x i32> @test_int_x86_vsm4key4128(<4 x i32> %A, <4 x i32> %B) {
6; CHECK-LABEL: test_int_x86_vsm4key4128:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsm4key4 %xmm1, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x7a,0xda,0xc1]
9; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
10  %ret = call <4 x i32> @llvm.x86.vsm4key4128(<4 x i32> %A, <4 x i32> %B)
11  ret <4 x i32> %ret
12}
13declare <4 x i32> @llvm.x86.vsm4key4128(<4 x i32> %A, <4 x i32> %B)
14
15define <8 x i32> @test_int_x86_vsm4key4256(<8 x i32> %A, <8 x i32> %B) {
16; CHECK-LABEL: test_int_x86_vsm4key4256:
17; CHECK:       # %bb.0:
18; CHECK-NEXT:    vsm4key4 %ymm1, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7e,0xda,0xc1]
19; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
20  %ret = call <8 x i32> @llvm.x86.vsm4key4256(<8 x i32> %A, <8 x i32> %B)
21  ret <8 x i32> %ret
22}
23declare <8 x i32> @llvm.x86.vsm4key4256(<8 x i32> %A, <8 x i32> %B)
24
25define <4 x i32> @test_int_x86_vsm4rnds4128(<4 x i32> %A, <4 x i32> %B) {
26; CHECK-LABEL: test_int_x86_vsm4rnds4128:
27; CHECK:       # %bb.0:
28; CHECK-NEXT:    vsm4rnds4 %xmm1, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x7b,0xda,0xc1]
29; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
30  %ret = call <4 x i32> @llvm.x86.vsm4rnds4128(<4 x i32> %A, <4 x i32> %B)
31  ret <4 x i32> %ret
32}
33declare <4 x i32> @llvm.x86.vsm4rnds4128(<4 x i32> %A, <4 x i32> %B)
34
35define <8 x i32> @test_int_x86_vsm4rnds4256(<8 x i32> %A, <8 x i32> %B) {
36; CHECK-LABEL: test_int_x86_vsm4rnds4256:
37; CHECK:       # %bb.0:
38; CHECK-NEXT:    vsm4rnds4 %ymm1, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xda,0xc1]
39; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
40  %ret = call <8 x i32> @llvm.x86.vsm4rnds4256(<8 x i32> %A, <8 x i32> %B)
41  ret <8 x i32> %ret
42}
43declare <8 x i32> @llvm.x86.vsm4rnds4256(<8 x i32> %A, <8 x i32> %B)
44