xref: /llvm-project/llvm/test/CodeGen/X86/sext-subreg.ll (revision 63ceb9afc693209964efd4ac4844c9c0712c312d)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
3; rdar://7529457
4
5define i64 @t(i64 %A, i64 %B, ptr %P, ptr%P2) nounwind {
6; CHECK-LABEL: t:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    addq %rsi, %rdi
9; CHECK-NEXT:    movl %edi, (%rdx)
10; CHECK-NEXT:    movslq %edi, %rax
11; CHECK-NEXT:    movq %rax, (%rcx)
12; CHECK-NEXT:    movl %eax, (%rdx)
13; CHECK-NEXT:    retq
14  %C = add i64 %A, %B
15  %D = trunc i64 %C to i32
16  store volatile i32 %D, ptr %P
17  %E = shl i64 %C, 32
18  %F = ashr i64 %E, 32
19  store volatile i64 %F, ptr%P2
20  store volatile i32 %D, ptr %P
21  ret i64 undef
22}
23