xref: /llvm-project/llvm/test/CodeGen/X86/sext-i1.ll (revision 3ab5dbb1995982ab7d106e39a719daaea8bdfeee)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i386-unknown-unknown -disable-cgp-branch-opts    | FileCheck %s --check-prefix=X86
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -disable-cgp-branch-opts  | FileCheck %s --check-prefix=X64
4
5; rdar://7573216
6; PR6146
7
8define i32 @t1(i32 %x) nounwind readnone ssp {
9; X86-LABEL: t1:
10; X86:       # %bb.0:
11; X86-NEXT:    xorl %eax, %eax
12; X86-NEXT:    cmpl $1, {{[0-9]+}}(%esp)
13; X86-NEXT:    sbbl %eax, %eax
14; X86-NEXT:    retl
15;
16; X64-LABEL: t1:
17; X64:       # %bb.0:
18; X64-NEXT:    xorl %eax, %eax
19; X64-NEXT:    cmpl $1, %edi
20; X64-NEXT:    sbbl %eax, %eax
21; X64-NEXT:    retq
22  %t0 = icmp eq i32 %x, 0
23  %if = select i1 %t0, i32 -1, i32 0
24  ret i32 %if
25}
26
27define i32 @t2(i32 %x) nounwind readnone ssp {
28; X86-LABEL: t2:
29; X86:       # %bb.0:
30; X86-NEXT:    xorl %eax, %eax
31; X86-NEXT:    cmpl $1, {{[0-9]+}}(%esp)
32; X86-NEXT:    sbbl %eax, %eax
33; X86-NEXT:    retl
34;
35; X64-LABEL: t2:
36; X64:       # %bb.0:
37; X64-NEXT:    xorl %eax, %eax
38; X64-NEXT:    cmpl $1, %edi
39; X64-NEXT:    sbbl %eax, %eax
40; X64-NEXT:    retq
41  %t0 = icmp eq i32 %x, 0
42  %if = sext i1 %t0 to i32
43  ret i32 %if
44}
45
46define i32 @t3(i32 %x, i64 %y) nounwind readonly {
47; X86-LABEL: t3:
48; X86:       # %bb.0: # %entry
49; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
50; X86-NEXT:    xorl %ecx, %ecx
51; X86-NEXT:    cmpl $1, {{[0-9]+}}(%esp)
52; X86-NEXT:    sbbl %ecx, %ecx
53; X86-NEXT:    cmpl %ecx, {{[0-9]+}}(%esp)
54; X86-NEXT:    sbbl %ecx, %eax
55; X86-NEXT:    xorl %eax, %eax
56; X86-NEXT:    retl
57;
58; X64-LABEL: t3:
59; X64:       # %bb.0: # %entry
60; X64-NEXT:    xorl %eax, %eax
61; X64-NEXT:    testl %edi, %edi
62; X64-NEXT:    sete %al
63; X64-NEXT:    negq %rax
64; X64-NEXT:    cmpq %rax, %rsi
65; X64-NEXT:    xorl %eax, %eax
66; X64-NEXT:    retq
67entry:
68  %not.tobool = icmp eq i32 %x, 0
69  %cond = sext i1 %not.tobool to i32
70  %conv = sext i1 %not.tobool to i64
71  %add13 = add i64 0, %conv
72  %cmp = icmp ult i64 %y, %add13
73  br i1 %cmp, label %if.then, label %if.end
74
75if.then:
76  br label %if.end
77
78if.end:
79  %xor27 = xor i32 undef, %cond
80  ret i32 0
81}
82
83define i32 @t4(i64 %x) nounwind readnone ssp {
84; X86-LABEL: t4:
85; X86:       # %bb.0:
86; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
87; X86-NEXT:    xorl %eax, %eax
88; X86-NEXT:    orl {{[0-9]+}}(%esp), %ecx
89; X86-NEXT:    sete %al
90; X86-NEXT:    negl %eax
91; X86-NEXT:    retl
92;
93; X64-LABEL: t4:
94; X64:       # %bb.0:
95; X64-NEXT:    xorl %eax, %eax
96; X64-NEXT:    cmpq $1, %rdi
97; X64-NEXT:    sbbl %eax, %eax
98; X64-NEXT:    retq
99  %t0 = icmp eq i64 %x, 0
100  %t1 = sext i1 %t0 to i32
101  ret i32 %t1
102}
103
104define i64 @t5(i32 %x) nounwind readnone ssp {
105; X86-LABEL: t5:
106; X86:       # %bb.0:
107; X86-NEXT:    xorl %eax, %eax
108; X86-NEXT:    cmpl $1, {{[0-9]+}}(%esp)
109; X86-NEXT:    sbbl %eax, %eax
110; X86-NEXT:    movl %eax, %edx
111; X86-NEXT:    retl
112;
113; X64-LABEL: t5:
114; X64:       # %bb.0:
115; X64-NEXT:    xorl %eax, %eax
116; X64-NEXT:    cmpl $1, %edi
117; X64-NEXT:    sbbq %rax, %rax
118; X64-NEXT:    retq
119  %t0 = icmp eq i32 %x, 0
120  %t1 = sext i1 %t0 to i64
121  ret i64 %t1
122}
123
124; sext (xor Bool, -1) --> sub (zext Bool), 1
125
126define i32 @select_0_or_1s(i1 %cond) {
127; X86-LABEL: select_0_or_1s:
128; X86:       # %bb.0:
129; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
130; X86-NEXT:    andl $1, %eax
131; X86-NEXT:    decl %eax
132; X86-NEXT:    retl
133;
134; X64-LABEL: select_0_or_1s:
135; X64:       # %bb.0:
136; X64-NEXT:    # kill: def $edi killed $edi def $rdi
137; X64-NEXT:    andl $1, %edi
138; X64-NEXT:    leal -1(%rdi), %eax
139; X64-NEXT:    retq
140  %not = xor i1 %cond, 1
141  %sext = sext i1 %not to i32
142  ret i32 %sext
143}
144
145; sext (xor Bool, -1) --> sub (zext Bool), 1
146
147define i32 @select_0_or_1s_zeroext(i1 zeroext %cond) {
148; X86-LABEL: select_0_or_1s_zeroext:
149; X86:       # %bb.0:
150; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
151; X86-NEXT:    decl %eax
152; X86-NEXT:    retl
153;
154; X64-LABEL: select_0_or_1s_zeroext:
155; X64:       # %bb.0:
156; X64-NEXT:    # kill: def $edi killed $edi def $rdi
157; X64-NEXT:    leal -1(%rdi), %eax
158; X64-NEXT:    retq
159  %not = xor i1 %cond, 1
160  %sext = sext i1 %not to i32
161  ret i32 %sext
162}
163
164; sext (xor Bool, -1) --> sub (zext Bool), 1
165
166define i32 @select_0_or_1s_signext(i1 signext %cond) {
167; X86-LABEL: select_0_or_1s_signext:
168; X86:       # %bb.0:
169; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
170; X86-NEXT:    andl $1, %eax
171; X86-NEXT:    decl %eax
172; X86-NEXT:    retl
173;
174; X64-LABEL: select_0_or_1s_signext:
175; X64:       # %bb.0:
176; X64-NEXT:    movl %edi, %eax
177; X64-NEXT:    notl %eax
178; X64-NEXT:    retq
179  %not = xor i1 %cond, 1
180  %sext = sext i1 %not to i32
181  ret i32 %sext
182}
183
184define i32 @zext_decrement_sext(i8 %x) {
185; X86-LABEL: zext_decrement_sext:
186; X86:       # %bb.0:
187; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
188; X86-NEXT:    decl %eax
189; X86-NEXT:    retl
190;
191; X64-LABEL: zext_decrement_sext:
192; X64:       # %bb.0:
193; X64-NEXT:    movzbl %dil, %eax
194; X64-NEXT:    decl %eax
195; X64-NEXT:    retq
196  %z = zext i8 %x to i16
197  %dec = add i16 %z, -1
198  %r = sext i16 %dec to i32
199  ret i32 %r
200}
201
202