1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s 3 4define i8 @isnonneg_i8(i8 %x) { 5; CHECK-LABEL: isnonneg_i8: 6; CHECK: # %bb.0: 7; CHECK-NEXT: movl %edi, %eax 8; CHECK-NEXT: sarb $7, %al 9; CHECK-NEXT: orb $42, %al 10; CHECK-NEXT: # kill: def $al killed $al killed $eax 11; CHECK-NEXT: retq 12 %cond = icmp sgt i8 %x, -1 13 %r = select i1 %cond, i8 42, i8 -1 14 ret i8 %r 15} 16 17define i16 @isnonneg_i16(i16 %x) { 18; CHECK-LABEL: isnonneg_i16: 19; CHECK: # %bb.0: 20; CHECK-NEXT: movswl %di, %eax 21; CHECK-NEXT: sarl $15, %eax 22; CHECK-NEXT: orl $542, %eax # imm = 0x21E 23; CHECK-NEXT: # kill: def $ax killed $ax killed $eax 24; CHECK-NEXT: retq 25 %cond = icmp sgt i16 %x, -1 26 %r = select i1 %cond, i16 542, i16 -1 27 ret i16 %r 28} 29 30define i32 @isnonneg_i32(i32 %x) { 31; CHECK-LABEL: isnonneg_i32: 32; CHECK: # %bb.0: 33; CHECK-NEXT: movl %edi, %eax 34; CHECK-NEXT: sarl $31, %eax 35; CHECK-NEXT: orl $-42, %eax 36; CHECK-NEXT: retq 37 %cond = icmp sgt i32 %x, -1 38 %r = select i1 %cond, i32 -42, i32 -1 39 ret i32 %r 40} 41 42define i64 @isnonneg_i64(i64 %x) { 43; CHECK-LABEL: isnonneg_i64: 44; CHECK: # %bb.0: 45; CHECK-NEXT: movq %rdi, %rax 46; CHECK-NEXT: sarq $63, %rax 47; CHECK-NEXT: orq $2342342, %rax # imm = 0x23BDC6 48; CHECK-NEXT: retq 49 %cond = icmp sgt i64 %x, -1 50 %r = select i1 %cond, i64 2342342, i64 -1 51 ret i64 %r 52} 53 54define <16 x i8> @isnonneg_v16i8(<16 x i8> %x) { 55; CHECK-LABEL: isnonneg_v16i8: 56; CHECK: # %bb.0: 57; CHECK-NEXT: pxor %xmm1, %xmm1 58; CHECK-NEXT: pcmpgtb %xmm0, %xmm1 59; CHECK-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 60; CHECK-NEXT: movdqa %xmm1, %xmm0 61; CHECK-NEXT: retq 62 %cond = icmp sgt <16 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 63 %r = select <16 x i1> %cond, <16 x i8> <i8 12, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 64 ret <16 x i8> %r 65} 66 67define <8 x i16> @isnonneg_v8i16(<8 x i16> %x) { 68; CHECK-LABEL: isnonneg_v8i16: 69; CHECK: # %bb.0: 70; CHECK-NEXT: psraw $15, %xmm0 71; CHECK-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 72; CHECK-NEXT: retq 73 %cond = icmp sgt <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 74 %r = select <8 x i1> %cond, <8 x i16> <i16 1, i16 542, i16 542, i16 542, i16 542, i16 542, i16 542, i16 1>, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 75 ret <8 x i16> %r 76} 77 78define <4 x i32> @isnonneg_v4i32(<4 x i32> %x) { 79; CHECK-LABEL: isnonneg_v4i32: 80; CHECK: # %bb.0: 81; CHECK-NEXT: psrad $31, %xmm0 82; CHECK-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 83; CHECK-NEXT: retq 84 %cond = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> 85 %r = select <4 x i1> %cond, <4 x i32> <i32 0, i32 42, i32 -42, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 86 ret <4 x i32> %r 87} 88 89define <2 x i64> @isnonneg_v2i64(<2 x i64> %x) { 90; CHECK-LABEL: isnonneg_v2i64: 91; CHECK: # %bb.0: 92; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] 93; CHECK-NEXT: psrad $31, %xmm0 94; CHECK-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 95; CHECK-NEXT: retq 96 %cond = icmp sgt <2 x i64> %x, <i64 -1, i64 -1> 97 %r = select <2 x i1> %cond, <2 x i64> <i64 2342342, i64 12>, <2 x i64> <i64 -1, i64 -1> 98 ret <2 x i64> %r 99} 100 101define i8 @isneg_i8(i8 %x) { 102; CHECK-LABEL: isneg_i8: 103; CHECK: # %bb.0: 104; CHECK-NEXT: movl %edi, %eax 105; CHECK-NEXT: sarb $7, %al 106; CHECK-NEXT: andb $42, %al 107; CHECK-NEXT: # kill: def $al killed $al killed $eax 108; CHECK-NEXT: retq 109 %cond = icmp slt i8 %x, 0 110 %r = select i1 %cond, i8 42, i8 0 111 ret i8 %r 112} 113 114define i16 @isneg_i16(i16 %x) { 115; CHECK-LABEL: isneg_i16: 116; CHECK: # %bb.0: 117; CHECK-NEXT: movswl %di, %eax 118; CHECK-NEXT: shrl $15, %eax 119; CHECK-NEXT: andl $542, %eax # imm = 0x21E 120; CHECK-NEXT: # kill: def $ax killed $ax killed $eax 121; CHECK-NEXT: retq 122 %cond = icmp slt i16 %x, 0 123 %r = select i1 %cond, i16 542, i16 0 124 ret i16 %r 125} 126 127define i32 @isneg_i32(i32 %x) { 128; CHECK-LABEL: isneg_i32: 129; CHECK: # %bb.0: 130; CHECK-NEXT: movl %edi, %eax 131; CHECK-NEXT: sarl $31, %eax 132; CHECK-NEXT: andl $-42, %eax 133; CHECK-NEXT: retq 134 %cond = icmp slt i32 %x, 0 135 %r = select i1 %cond, i32 -42, i32 0 136 ret i32 %r 137} 138 139define i64 @isneg_i64(i64 %x) { 140; CHECK-LABEL: isneg_i64: 141; CHECK: # %bb.0: 142; CHECK-NEXT: movq %rdi, %rax 143; CHECK-NEXT: sarq $63, %rax 144; CHECK-NEXT: andl $2342342, %eax # imm = 0x23BDC6 145; CHECK-NEXT: retq 146 %cond = icmp slt i64 %x, 0 147 %r = select i1 %cond, i64 2342342, i64 0 148 ret i64 %r 149} 150 151define <16 x i8> @isneg_v16i8(<16 x i8> %x) { 152; CHECK-LABEL: isneg_v16i8: 153; CHECK: # %bb.0: 154; CHECK-NEXT: pxor %xmm1, %xmm1 155; CHECK-NEXT: pcmpgtb %xmm0, %xmm1 156; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 157; CHECK-NEXT: movdqa %xmm1, %xmm0 158; CHECK-NEXT: retq 159 %cond = icmp slt <16 x i8> %x, zeroinitializer 160 %r = select <16 x i1> %cond, <16 x i8> <i8 12, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>, <16 x i8> zeroinitializer 161 ret <16 x i8> %r 162} 163 164define <8 x i16> @isneg_v8i16(<8 x i16> %x) { 165; CHECK-LABEL: isneg_v8i16: 166; CHECK: # %bb.0: 167; CHECK-NEXT: psraw $15, %xmm0 168; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 169; CHECK-NEXT: retq 170 %cond = icmp slt <8 x i16> %x, zeroinitializer 171 %r = select <8 x i1> %cond, <8 x i16> <i16 1, i16 542, i16 542, i16 542, i16 542, i16 542, i16 542, i16 1>, <8 x i16> zeroinitializer 172 ret <8 x i16> %r 173} 174 175define <4 x i32> @isneg_v4i32(<4 x i32> %x) { 176; CHECK-LABEL: isneg_v4i32: 177; CHECK: # %bb.0: 178; CHECK-NEXT: psrad $31, %xmm0 179; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 180; CHECK-NEXT: retq 181 %cond = icmp slt <4 x i32> %x, zeroinitializer 182 %r = select <4 x i1> %cond, <4 x i32> <i32 0, i32 42, i32 -42, i32 1>, <4 x i32> zeroinitializer 183 ret <4 x i32> %r 184} 185 186define <2 x i64> @isneg_v2i64(<2 x i64> %x) { 187; CHECK-LABEL: isneg_v2i64: 188; CHECK: # %bb.0: 189; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] 190; CHECK-NEXT: psrad $31, %xmm0 191; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 192; CHECK-NEXT: retq 193 %cond = icmp slt <2 x i64> %x, zeroinitializer 194 %r = select <2 x i1> %cond, <2 x i64> <i64 2342342, i64 12>, <2 x i64> zeroinitializer 195 ret <2 x i64> %r 196} 197