xref: /llvm-project/llvm/test/CodeGen/X86/pull-conditional-binop-through-shift.ll (revision 88bd507dc2dd9c235b54d718cf84e4ef80d94bc9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
3; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
4
5; shift left
6
7define i32 @and_signbit_select_shl(i32 %x, i1 %cond, ptr %dst) {
8; X64-LABEL: and_signbit_select_shl:
9; X64:       # %bb.0:
10; X64-NEXT:    movl %edi, %eax
11; X64-NEXT:    andl $16711680, %eax # imm = 0xFF0000
12; X64-NEXT:    testb $1, %sil
13; X64-NEXT:    cmovel %edi, %eax
14; X64-NEXT:    shll $8, %eax
15; X64-NEXT:    movl %eax, (%rdx)
16; X64-NEXT:    retq
17;
18; X86-LABEL: and_signbit_select_shl:
19; X86:       # %bb.0:
20; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
21; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
22; X86-NEXT:    testb $1, {{[0-9]+}}(%esp)
23; X86-NEXT:    je .LBB0_2
24; X86-NEXT:  # %bb.1:
25; X86-NEXT:    andl $16711680, %eax # imm = 0xFF0000
26; X86-NEXT:  .LBB0_2:
27; X86-NEXT:    shll $8, %eax
28; X86-NEXT:    movl %eax, (%ecx)
29; X86-NEXT:    retl
30  %t0 = and i32 %x, 4294901760 ; 0xFFFF0000
31  %t1 = select i1 %cond, i32 %t0, i32 %x
32  %r = shl i32 %t1, 8
33  store i32 %r, ptr %dst
34  ret i32 %r
35}
36define i32 @and_nosignbit_select_shl(i32 %x, i1 %cond, ptr %dst) {
37; X64-LABEL: and_nosignbit_select_shl:
38; X64:       # %bb.0:
39; X64-NEXT:    movl %edi, %eax
40; X64-NEXT:    andl $16711680, %eax # imm = 0xFF0000
41; X64-NEXT:    testb $1, %sil
42; X64-NEXT:    cmovel %edi, %eax
43; X64-NEXT:    shll $8, %eax
44; X64-NEXT:    movl %eax, (%rdx)
45; X64-NEXT:    retq
46;
47; X86-LABEL: and_nosignbit_select_shl:
48; X86:       # %bb.0:
49; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
50; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
51; X86-NEXT:    testb $1, {{[0-9]+}}(%esp)
52; X86-NEXT:    je .LBB1_2
53; X86-NEXT:  # %bb.1:
54; X86-NEXT:    andl $16711680, %eax # imm = 0xFF0000
55; X86-NEXT:  .LBB1_2:
56; X86-NEXT:    shll $8, %eax
57; X86-NEXT:    movl %eax, (%ecx)
58; X86-NEXT:    retl
59  %t0 = and i32 %x, 2147418112 ; 0x7FFF0000
60  %t1 = select i1 %cond, i32 %t0, i32 %x
61  %r = shl i32 %t1, 8
62  store i32 %r, ptr %dst
63  ret i32 %r
64}
65
66define i32 @or_signbit_select_shl(i32 %x, i1 %cond, ptr %dst) {
67; X64-LABEL: or_signbit_select_shl:
68; X64:       # %bb.0:
69; X64-NEXT:    movl %edi, %eax
70; X64-NEXT:    orl $16711680, %eax # imm = 0xFF0000
71; X64-NEXT:    testb $1, %sil
72; X64-NEXT:    cmovel %edi, %eax
73; X64-NEXT:    shll $8, %eax
74; X64-NEXT:    movl %eax, (%rdx)
75; X64-NEXT:    retq
76;
77; X86-LABEL: or_signbit_select_shl:
78; X86:       # %bb.0:
79; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
80; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
81; X86-NEXT:    andl $1, %eax
82; X86-NEXT:    negl %eax
83; X86-NEXT:    andl $16711680, %eax # imm = 0xFF0000
84; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
85; X86-NEXT:    shll $8, %eax
86; X86-NEXT:    movl %eax, (%ecx)
87; X86-NEXT:    retl
88  %t0 = or i32 %x, 4294901760 ; 0xFFFF0000
89  %t1 = select i1 %cond, i32 %t0, i32 %x
90  %r = shl i32 %t1, 8
91  store i32 %r, ptr %dst
92  ret i32 %r
93}
94define i32 @or_nosignbit_select_shl(i32 %x, i1 %cond, ptr %dst) {
95; X64-LABEL: or_nosignbit_select_shl:
96; X64:       # %bb.0:
97; X64-NEXT:    movl %edi, %eax
98; X64-NEXT:    orl $16711680, %eax # imm = 0xFF0000
99; X64-NEXT:    testb $1, %sil
100; X64-NEXT:    cmovel %edi, %eax
101; X64-NEXT:    shll $8, %eax
102; X64-NEXT:    movl %eax, (%rdx)
103; X64-NEXT:    retq
104;
105; X86-LABEL: or_nosignbit_select_shl:
106; X86:       # %bb.0:
107; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
108; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
109; X86-NEXT:    andl $1, %eax
110; X86-NEXT:    negl %eax
111; X86-NEXT:    andl $16711680, %eax # imm = 0xFF0000
112; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
113; X86-NEXT:    shll $8, %eax
114; X86-NEXT:    movl %eax, (%ecx)
115; X86-NEXT:    retl
116  %t0 = or i32 %x, 2147418112 ; 0x7FFF0000
117  %t1 = select i1 %cond, i32 %t0, i32 %x
118  %r = shl i32 %t1, 8
119  store i32 %r, ptr %dst
120  ret i32 %r
121}
122
123define i32 @xor_signbit_select_shl(i32 %x, i1 %cond, ptr %dst) {
124; X64-LABEL: xor_signbit_select_shl:
125; X64:       # %bb.0:
126; X64-NEXT:    movl %edi, %eax
127; X64-NEXT:    xorl $16711680, %eax # imm = 0xFF0000
128; X64-NEXT:    testb $1, %sil
129; X64-NEXT:    cmovel %edi, %eax
130; X64-NEXT:    shll $8, %eax
131; X64-NEXT:    movl %eax, (%rdx)
132; X64-NEXT:    retq
133;
134; X86-LABEL: xor_signbit_select_shl:
135; X86:       # %bb.0:
136; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
137; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
138; X86-NEXT:    andl $1, %eax
139; X86-NEXT:    negl %eax
140; X86-NEXT:    andl $16711680, %eax # imm = 0xFF0000
141; X86-NEXT:    xorl {{[0-9]+}}(%esp), %eax
142; X86-NEXT:    shll $8, %eax
143; X86-NEXT:    movl %eax, (%ecx)
144; X86-NEXT:    retl
145  %t0 = xor i32 %x, 4294901760 ; 0xFFFF0000
146  %t1 = select i1 %cond, i32 %t0, i32 %x
147  %r = shl i32 %t1, 8
148  store i32 %r, ptr %dst
149  ret i32 %r
150}
151define i32 @xor_nosignbit_select_shl(i32 %x, i1 %cond, ptr %dst) {
152; X64-LABEL: xor_nosignbit_select_shl:
153; X64:       # %bb.0:
154; X64-NEXT:    movl %edi, %eax
155; X64-NEXT:    xorl $16711680, %eax # imm = 0xFF0000
156; X64-NEXT:    testb $1, %sil
157; X64-NEXT:    cmovel %edi, %eax
158; X64-NEXT:    shll $8, %eax
159; X64-NEXT:    movl %eax, (%rdx)
160; X64-NEXT:    retq
161;
162; X86-LABEL: xor_nosignbit_select_shl:
163; X86:       # %bb.0:
164; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
165; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
166; X86-NEXT:    andl $1, %eax
167; X86-NEXT:    negl %eax
168; X86-NEXT:    andl $16711680, %eax # imm = 0xFF0000
169; X86-NEXT:    xorl {{[0-9]+}}(%esp), %eax
170; X86-NEXT:    shll $8, %eax
171; X86-NEXT:    movl %eax, (%ecx)
172; X86-NEXT:    retl
173  %t0 = xor i32 %x, 2147418112 ; 0x7FFF0000
174  %t1 = select i1 %cond, i32 %t0, i32 %x
175  %r = shl i32 %t1, 8
176  store i32 %r, ptr %dst
177  ret i32 %r
178}
179
180define i32 @add_signbit_select_shl(i32 %x, i1 %cond, ptr %dst) {
181; X64-LABEL: add_signbit_select_shl:
182; X64:       # %bb.0:
183; X64-NEXT:    # kill: def $edi killed $edi def $rdi
184; X64-NEXT:    leal -65536(%rdi), %eax
185; X64-NEXT:    testb $1, %sil
186; X64-NEXT:    cmovel %edi, %eax
187; X64-NEXT:    shll $8, %eax
188; X64-NEXT:    movl %eax, (%rdx)
189; X64-NEXT:    retq
190;
191; X86-LABEL: add_signbit_select_shl:
192; X86:       # %bb.0:
193; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
194; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
195; X86-NEXT:    andl $1, %eax
196; X86-NEXT:    negl %eax
197; X86-NEXT:    andl $16711680, %eax # imm = 0xFF0000
198; X86-NEXT:    addl {{[0-9]+}}(%esp), %eax
199; X86-NEXT:    shll $8, %eax
200; X86-NEXT:    movl %eax, (%ecx)
201; X86-NEXT:    retl
202  %t0 = add i32 %x, 4294901760 ; 0xFFFF0000
203  %t1 = select i1 %cond, i32 %t0, i32 %x
204  %r = shl i32 %t1, 8
205  store i32 %r, ptr %dst
206  ret i32 %r
207}
208define i32 @add_nosignbit_select_shl(i32 %x, i1 %cond, ptr %dst) {
209; X64-LABEL: add_nosignbit_select_shl:
210; X64:       # %bb.0:
211; X64-NEXT:    # kill: def $edi killed $edi def $rdi
212; X64-NEXT:    leal 2147418112(%rdi), %eax
213; X64-NEXT:    testb $1, %sil
214; X64-NEXT:    cmovel %edi, %eax
215; X64-NEXT:    shll $8, %eax
216; X64-NEXT:    movl %eax, (%rdx)
217; X64-NEXT:    retq
218;
219; X86-LABEL: add_nosignbit_select_shl:
220; X86:       # %bb.0:
221; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
222; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
223; X86-NEXT:    andl $1, %eax
224; X86-NEXT:    negl %eax
225; X86-NEXT:    andl $16711680, %eax # imm = 0xFF0000
226; X86-NEXT:    addl {{[0-9]+}}(%esp), %eax
227; X86-NEXT:    shll $8, %eax
228; X86-NEXT:    movl %eax, (%ecx)
229; X86-NEXT:    retl
230  %t0 = add i32 %x, 2147418112 ; 0x7FFF0000
231  %t1 = select i1 %cond, i32 %t0, i32 %x
232  %r = shl i32 %t1, 8
233  store i32 %r, ptr %dst
234  ret i32 %r
235}
236
237; logical shift right
238
239define i32 @and_signbit_select_lshr(i32 %x, i1 %cond, ptr %dst) {
240; X64-LABEL: and_signbit_select_lshr:
241; X64:       # %bb.0:
242; X64-NEXT:    movl %edi, %eax
243; X64-NEXT:    andl $-65536, %eax # imm = 0xFFFF0000
244; X64-NEXT:    testb $1, %sil
245; X64-NEXT:    cmovel %edi, %eax
246; X64-NEXT:    shrl $8, %eax
247; X64-NEXT:    movl %eax, (%rdx)
248; X64-NEXT:    retq
249;
250; X86-LABEL: and_signbit_select_lshr:
251; X86:       # %bb.0:
252; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
253; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
254; X86-NEXT:    testb $1, {{[0-9]+}}(%esp)
255; X86-NEXT:    je .LBB8_2
256; X86-NEXT:  # %bb.1:
257; X86-NEXT:    andl $-65536, %eax # imm = 0xFFFF0000
258; X86-NEXT:  .LBB8_2:
259; X86-NEXT:    shrl $8, %eax
260; X86-NEXT:    movl %eax, (%ecx)
261; X86-NEXT:    retl
262  %t0 = and i32 %x, 4294901760 ; 0xFFFF0000
263  %t1 = select i1 %cond, i32 %t0, i32 %x
264  %r = lshr i32 %t1, 8
265  store i32 %r, ptr %dst
266  ret i32 %r
267}
268define i32 @and_nosignbit_select_lshr(i32 %x, i1 %cond, ptr %dst) {
269; X64-LABEL: and_nosignbit_select_lshr:
270; X64:       # %bb.0:
271; X64-NEXT:    movl %edi, %eax
272; X64-NEXT:    andl $2147418112, %eax # imm = 0x7FFF0000
273; X64-NEXT:    testb $1, %sil
274; X64-NEXT:    cmovel %edi, %eax
275; X64-NEXT:    shrl $8, %eax
276; X64-NEXT:    movl %eax, (%rdx)
277; X64-NEXT:    retq
278;
279; X86-LABEL: and_nosignbit_select_lshr:
280; X86:       # %bb.0:
281; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
282; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
283; X86-NEXT:    testb $1, {{[0-9]+}}(%esp)
284; X86-NEXT:    je .LBB9_2
285; X86-NEXT:  # %bb.1:
286; X86-NEXT:    andl $2147418112, %eax # imm = 0x7FFF0000
287; X86-NEXT:  .LBB9_2:
288; X86-NEXT:    shrl $8, %eax
289; X86-NEXT:    movl %eax, (%ecx)
290; X86-NEXT:    retl
291  %t0 = and i32 %x, 2147418112 ; 0x7FFF0000
292  %t1 = select i1 %cond, i32 %t0, i32 %x
293  %r = lshr i32 %t1, 8
294  store i32 %r, ptr %dst
295  ret i32 %r
296}
297
298define i32 @or_signbit_select_lshr(i32 %x, i1 %cond, ptr %dst) {
299; X64-LABEL: or_signbit_select_lshr:
300; X64:       # %bb.0:
301; X64-NEXT:    movl %edi, %eax
302; X64-NEXT:    orl $-65536, %eax # imm = 0xFFFF0000
303; X64-NEXT:    testb $1, %sil
304; X64-NEXT:    cmovel %edi, %eax
305; X64-NEXT:    shrl $8, %eax
306; X64-NEXT:    movl %eax, (%rdx)
307; X64-NEXT:    retq
308;
309; X86-LABEL: or_signbit_select_lshr:
310; X86:       # %bb.0:
311; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
312; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
313; X86-NEXT:    andl $1, %eax
314; X86-NEXT:    negl %eax
315; X86-NEXT:    andl $-65536, %eax # imm = 0xFFFF0000
316; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
317; X86-NEXT:    shrl $8, %eax
318; X86-NEXT:    movl %eax, (%ecx)
319; X86-NEXT:    retl
320  %t0 = or i32 %x, 4294901760 ; 0xFFFF0000
321  %t1 = select i1 %cond, i32 %t0, i32 %x
322  %r = lshr i32 %t1, 8
323  store i32 %r, ptr %dst
324  ret i32 %r
325}
326define i32 @or_nosignbit_select_lshr(i32 %x, i1 %cond, ptr %dst) {
327; X64-LABEL: or_nosignbit_select_lshr:
328; X64:       # %bb.0:
329; X64-NEXT:    movl %edi, %eax
330; X64-NEXT:    orl $2147418112, %eax # imm = 0x7FFF0000
331; X64-NEXT:    testb $1, %sil
332; X64-NEXT:    cmovel %edi, %eax
333; X64-NEXT:    shrl $8, %eax
334; X64-NEXT:    movl %eax, (%rdx)
335; X64-NEXT:    retq
336;
337; X86-LABEL: or_nosignbit_select_lshr:
338; X86:       # %bb.0:
339; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
340; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
341; X86-NEXT:    andl $1, %eax
342; X86-NEXT:    negl %eax
343; X86-NEXT:    andl $2147418112, %eax # imm = 0x7FFF0000
344; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
345; X86-NEXT:    shrl $8, %eax
346; X86-NEXT:    movl %eax, (%ecx)
347; X86-NEXT:    retl
348  %t0 = or i32 %x, 2147418112 ; 0x7FFF0000
349  %t1 = select i1 %cond, i32 %t0, i32 %x
350  %r = lshr i32 %t1, 8
351  store i32 %r, ptr %dst
352  ret i32 %r
353}
354
355define i32 @xor_signbit_select_lshr(i32 %x, i1 %cond, ptr %dst) {
356; X64-LABEL: xor_signbit_select_lshr:
357; X64:       # %bb.0:
358; X64-NEXT:    movl %edi, %eax
359; X64-NEXT:    xorl $-65536, %eax # imm = 0xFFFF0000
360; X64-NEXT:    testb $1, %sil
361; X64-NEXT:    cmovel %edi, %eax
362; X64-NEXT:    shrl $8, %eax
363; X64-NEXT:    movl %eax, (%rdx)
364; X64-NEXT:    retq
365;
366; X86-LABEL: xor_signbit_select_lshr:
367; X86:       # %bb.0:
368; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
369; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
370; X86-NEXT:    andl $1, %eax
371; X86-NEXT:    negl %eax
372; X86-NEXT:    andl $-65536, %eax # imm = 0xFFFF0000
373; X86-NEXT:    xorl {{[0-9]+}}(%esp), %eax
374; X86-NEXT:    shrl $8, %eax
375; X86-NEXT:    movl %eax, (%ecx)
376; X86-NEXT:    retl
377  %t0 = xor i32 %x, 4294901760 ; 0xFFFF0000
378  %t1 = select i1 %cond, i32 %t0, i32 %x
379  %r = lshr i32 %t1, 8
380  store i32 %r, ptr %dst
381  ret i32 %r
382}
383define i32 @xor_nosignbit_select_lshr(i32 %x, i1 %cond, ptr %dst) {
384; X64-LABEL: xor_nosignbit_select_lshr:
385; X64:       # %bb.0:
386; X64-NEXT:    movl %edi, %eax
387; X64-NEXT:    xorl $2147418112, %eax # imm = 0x7FFF0000
388; X64-NEXT:    testb $1, %sil
389; X64-NEXT:    cmovel %edi, %eax
390; X64-NEXT:    shrl $8, %eax
391; X64-NEXT:    movl %eax, (%rdx)
392; X64-NEXT:    retq
393;
394; X86-LABEL: xor_nosignbit_select_lshr:
395; X86:       # %bb.0:
396; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
397; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
398; X86-NEXT:    andl $1, %eax
399; X86-NEXT:    negl %eax
400; X86-NEXT:    andl $2147418112, %eax # imm = 0x7FFF0000
401; X86-NEXT:    xorl {{[0-9]+}}(%esp), %eax
402; X86-NEXT:    shrl $8, %eax
403; X86-NEXT:    movl %eax, (%ecx)
404; X86-NEXT:    retl
405  %t0 = xor i32 %x, 2147418112 ; 0x7FFF0000
406  %t1 = select i1 %cond, i32 %t0, i32 %x
407  %r = lshr i32 %t1, 8
408  store i32 %r, ptr %dst
409  ret i32 %r
410}
411
412define i32 @add_signbit_select_lshr(i32 %x, i1 %cond, ptr %dst) {
413; X64-LABEL: add_signbit_select_lshr:
414; X64:       # %bb.0:
415; X64-NEXT:    # kill: def $edi killed $edi def $rdi
416; X64-NEXT:    leal -65536(%rdi), %eax
417; X64-NEXT:    testb $1, %sil
418; X64-NEXT:    cmovel %edi, %eax
419; X64-NEXT:    shrl $8, %eax
420; X64-NEXT:    movl %eax, (%rdx)
421; X64-NEXT:    retq
422;
423; X86-LABEL: add_signbit_select_lshr:
424; X86:       # %bb.0:
425; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
426; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
427; X86-NEXT:    andl $1, %eax
428; X86-NEXT:    negl %eax
429; X86-NEXT:    andl $-65536, %eax # imm = 0xFFFF0000
430; X86-NEXT:    addl {{[0-9]+}}(%esp), %eax
431; X86-NEXT:    shrl $8, %eax
432; X86-NEXT:    movl %eax, (%ecx)
433; X86-NEXT:    retl
434  %t0 = add i32 %x, 4294901760 ; 0xFFFF0000
435  %t1 = select i1 %cond, i32 %t0, i32 %x
436  %r = lshr i32 %t1, 8
437  store i32 %r, ptr %dst
438  ret i32 %r
439}
440define i32 @add_nosignbit_select_lshr(i32 %x, i1 %cond, ptr %dst) {
441; X64-LABEL: add_nosignbit_select_lshr:
442; X64:       # %bb.0:
443; X64-NEXT:    # kill: def $edi killed $edi def $rdi
444; X64-NEXT:    leal 2147418112(%rdi), %eax
445; X64-NEXT:    testb $1, %sil
446; X64-NEXT:    cmovel %edi, %eax
447; X64-NEXT:    shrl $8, %eax
448; X64-NEXT:    movl %eax, (%rdx)
449; X64-NEXT:    retq
450;
451; X86-LABEL: add_nosignbit_select_lshr:
452; X86:       # %bb.0:
453; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
454; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
455; X86-NEXT:    andl $1, %eax
456; X86-NEXT:    negl %eax
457; X86-NEXT:    andl $2147418112, %eax # imm = 0x7FFF0000
458; X86-NEXT:    addl {{[0-9]+}}(%esp), %eax
459; X86-NEXT:    shrl $8, %eax
460; X86-NEXT:    movl %eax, (%ecx)
461; X86-NEXT:    retl
462  %t0 = add i32 %x, 2147418112 ; 0x7FFF0000
463  %t1 = select i1 %cond, i32 %t0, i32 %x
464  %r = lshr i32 %t1, 8
465  store i32 %r, ptr %dst
466  ret i32 %r
467}
468
469; arithmetic shift right
470
471define i32 @and_signbit_select_ashr(i32 %x, i1 %cond, ptr %dst) {
472; X64-LABEL: and_signbit_select_ashr:
473; X64:       # %bb.0:
474; X64-NEXT:    movl %edi, %eax
475; X64-NEXT:    andl $-65536, %eax # imm = 0xFFFF0000
476; X64-NEXT:    testb $1, %sil
477; X64-NEXT:    cmovel %edi, %eax
478; X64-NEXT:    sarl $8, %eax
479; X64-NEXT:    movl %eax, (%rdx)
480; X64-NEXT:    retq
481;
482; X86-LABEL: and_signbit_select_ashr:
483; X86:       # %bb.0:
484; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
485; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
486; X86-NEXT:    testb $1, {{[0-9]+}}(%esp)
487; X86-NEXT:    je .LBB16_2
488; X86-NEXT:  # %bb.1:
489; X86-NEXT:    andl $-65536, %eax # imm = 0xFFFF0000
490; X86-NEXT:  .LBB16_2:
491; X86-NEXT:    sarl $8, %eax
492; X86-NEXT:    movl %eax, (%ecx)
493; X86-NEXT:    retl
494  %t0 = and i32 %x, 4294901760 ; 0xFFFF0000
495  %t1 = select i1 %cond, i32 %t0, i32 %x
496  %r = ashr i32 %t1, 8
497  store i32 %r, ptr %dst
498  ret i32 %r
499}
500define i32 @and_nosignbit_select_ashr(i32 %x, i1 %cond, ptr %dst) {
501; X64-LABEL: and_nosignbit_select_ashr:
502; X64:       # %bb.0:
503; X64-NEXT:    movl %edi, %eax
504; X64-NEXT:    andl $2147418112, %eax # imm = 0x7FFF0000
505; X64-NEXT:    testb $1, %sil
506; X64-NEXT:    cmovel %edi, %eax
507; X64-NEXT:    sarl $8, %eax
508; X64-NEXT:    movl %eax, (%rdx)
509; X64-NEXT:    retq
510;
511; X86-LABEL: and_nosignbit_select_ashr:
512; X86:       # %bb.0:
513; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
514; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
515; X86-NEXT:    testb $1, {{[0-9]+}}(%esp)
516; X86-NEXT:    je .LBB17_2
517; X86-NEXT:  # %bb.1:
518; X86-NEXT:    andl $2147418112, %eax # imm = 0x7FFF0000
519; X86-NEXT:  .LBB17_2:
520; X86-NEXT:    sarl $8, %eax
521; X86-NEXT:    movl %eax, (%ecx)
522; X86-NEXT:    retl
523  %t0 = and i32 %x, 2147418112 ; 0x7FFF0000
524  %t1 = select i1 %cond, i32 %t0, i32 %x
525  %r = ashr i32 %t1, 8
526  store i32 %r, ptr %dst
527  ret i32 %r
528}
529
530define i32 @or_signbit_select_ashr(i32 %x, i1 %cond, ptr %dst) {
531; X64-LABEL: or_signbit_select_ashr:
532; X64:       # %bb.0:
533; X64-NEXT:    movl %edi, %eax
534; X64-NEXT:    orl $-65536, %eax # imm = 0xFFFF0000
535; X64-NEXT:    testb $1, %sil
536; X64-NEXT:    cmovel %edi, %eax
537; X64-NEXT:    sarl $8, %eax
538; X64-NEXT:    movl %eax, (%rdx)
539; X64-NEXT:    retq
540;
541; X86-LABEL: or_signbit_select_ashr:
542; X86:       # %bb.0:
543; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
544; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
545; X86-NEXT:    andl $1, %eax
546; X86-NEXT:    negl %eax
547; X86-NEXT:    andl $-65536, %eax # imm = 0xFFFF0000
548; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
549; X86-NEXT:    sarl $8, %eax
550; X86-NEXT:    movl %eax, (%ecx)
551; X86-NEXT:    retl
552  %t0 = or i32 %x, 4294901760 ; 0xFFFF0000
553  %t1 = select i1 %cond, i32 %t0, i32 %x
554  %r = ashr i32 %t1, 8
555  store i32 %r, ptr %dst
556  ret i32 %r
557}
558define i32 @or_nosignbit_select_ashr(i32 %x, i1 %cond, ptr %dst) {
559; X64-LABEL: or_nosignbit_select_ashr:
560; X64:       # %bb.0:
561; X64-NEXT:    movl %edi, %eax
562; X64-NEXT:    orl $2147418112, %eax # imm = 0x7FFF0000
563; X64-NEXT:    testb $1, %sil
564; X64-NEXT:    cmovel %edi, %eax
565; X64-NEXT:    sarl $8, %eax
566; X64-NEXT:    movl %eax, (%rdx)
567; X64-NEXT:    retq
568;
569; X86-LABEL: or_nosignbit_select_ashr:
570; X86:       # %bb.0:
571; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
572; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
573; X86-NEXT:    andl $1, %eax
574; X86-NEXT:    negl %eax
575; X86-NEXT:    andl $2147418112, %eax # imm = 0x7FFF0000
576; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
577; X86-NEXT:    sarl $8, %eax
578; X86-NEXT:    movl %eax, (%ecx)
579; X86-NEXT:    retl
580  %t0 = or i32 %x, 2147418112 ; 0x7FFF0000
581  %t1 = select i1 %cond, i32 %t0, i32 %x
582  %r = ashr i32 %t1, 8
583  store i32 %r, ptr %dst
584  ret i32 %r
585}
586
587define i32 @xor_signbit_select_ashr(i32 %x, i1 %cond, ptr %dst) {
588; X64-LABEL: xor_signbit_select_ashr:
589; X64:       # %bb.0:
590; X64-NEXT:    movl %edi, %eax
591; X64-NEXT:    xorl $-65536, %eax # imm = 0xFFFF0000
592; X64-NEXT:    testb $1, %sil
593; X64-NEXT:    cmovel %edi, %eax
594; X64-NEXT:    sarl $8, %eax
595; X64-NEXT:    movl %eax, (%rdx)
596; X64-NEXT:    retq
597;
598; X86-LABEL: xor_signbit_select_ashr:
599; X86:       # %bb.0:
600; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
601; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
602; X86-NEXT:    andl $1, %eax
603; X86-NEXT:    negl %eax
604; X86-NEXT:    andl $-65536, %eax # imm = 0xFFFF0000
605; X86-NEXT:    xorl {{[0-9]+}}(%esp), %eax
606; X86-NEXT:    sarl $8, %eax
607; X86-NEXT:    movl %eax, (%ecx)
608; X86-NEXT:    retl
609  %t0 = xor i32 %x, 4294901760 ; 0xFFFF0000
610  %t1 = select i1 %cond, i32 %t0, i32 %x
611  %r = ashr i32 %t1, 8
612  store i32 %r, ptr %dst
613  ret i32 %r
614}
615define i32 @xor_nosignbit_select_ashr(i32 %x, i1 %cond, ptr %dst) {
616; X64-LABEL: xor_nosignbit_select_ashr:
617; X64:       # %bb.0:
618; X64-NEXT:    movl %edi, %eax
619; X64-NEXT:    xorl $2147418112, %eax # imm = 0x7FFF0000
620; X64-NEXT:    testb $1, %sil
621; X64-NEXT:    cmovel %edi, %eax
622; X64-NEXT:    sarl $8, %eax
623; X64-NEXT:    movl %eax, (%rdx)
624; X64-NEXT:    retq
625;
626; X86-LABEL: xor_nosignbit_select_ashr:
627; X86:       # %bb.0:
628; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
629; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
630; X86-NEXT:    andl $1, %eax
631; X86-NEXT:    negl %eax
632; X86-NEXT:    andl $2147418112, %eax # imm = 0x7FFF0000
633; X86-NEXT:    xorl {{[0-9]+}}(%esp), %eax
634; X86-NEXT:    sarl $8, %eax
635; X86-NEXT:    movl %eax, (%ecx)
636; X86-NEXT:    retl
637  %t0 = xor i32 %x, 2147418112 ; 0x7FFF0000
638  %t1 = select i1 %cond, i32 %t0, i32 %x
639  %r = ashr i32 %t1, 8
640  store i32 %r, ptr %dst
641  ret i32 %r
642}
643
644define i32 @add_signbit_select_ashr(i32 %x, i1 %cond, ptr %dst) {
645; X64-LABEL: add_signbit_select_ashr:
646; X64:       # %bb.0:
647; X64-NEXT:    # kill: def $edi killed $edi def $rdi
648; X64-NEXT:    leal -65536(%rdi), %eax
649; X64-NEXT:    testb $1, %sil
650; X64-NEXT:    cmovel %edi, %eax
651; X64-NEXT:    sarl $8, %eax
652; X64-NEXT:    movl %eax, (%rdx)
653; X64-NEXT:    retq
654;
655; X86-LABEL: add_signbit_select_ashr:
656; X86:       # %bb.0:
657; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
658; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
659; X86-NEXT:    andl $1, %eax
660; X86-NEXT:    negl %eax
661; X86-NEXT:    andl $-65536, %eax # imm = 0xFFFF0000
662; X86-NEXT:    addl {{[0-9]+}}(%esp), %eax
663; X86-NEXT:    sarl $8, %eax
664; X86-NEXT:    movl %eax, (%ecx)
665; X86-NEXT:    retl
666  %t0 = add i32 %x, 4294901760 ; 0xFFFF0000
667  %t1 = select i1 %cond, i32 %t0, i32 %x
668  %r = ashr i32 %t1, 8
669  store i32 %r, ptr %dst
670  ret i32 %r
671}
672define i32 @add_nosignbit_select_ashr(i32 %x, i1 %cond, ptr %dst) {
673; X64-LABEL: add_nosignbit_select_ashr:
674; X64:       # %bb.0:
675; X64-NEXT:    # kill: def $edi killed $edi def $rdi
676; X64-NEXT:    leal 2147418112(%rdi), %eax
677; X64-NEXT:    testb $1, %sil
678; X64-NEXT:    cmovel %edi, %eax
679; X64-NEXT:    sarl $8, %eax
680; X64-NEXT:    movl %eax, (%rdx)
681; X64-NEXT:    retq
682;
683; X86-LABEL: add_nosignbit_select_ashr:
684; X86:       # %bb.0:
685; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
686; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
687; X86-NEXT:    andl $1, %eax
688; X86-NEXT:    negl %eax
689; X86-NEXT:    andl $2147418112, %eax # imm = 0x7FFF0000
690; X86-NEXT:    addl {{[0-9]+}}(%esp), %eax
691; X86-NEXT:    sarl $8, %eax
692; X86-NEXT:    movl %eax, (%ecx)
693; X86-NEXT:    retl
694  %t0 = add i32 %x, 2147418112 ; 0x7FFF0000
695  %t1 = select i1 %cond, i32 %t0, i32 %x
696  %r = ashr i32 %t1, 8
697  store i32 %r, ptr %dst
698  ret i32 %r
699}
700
701define i32 @shl_signbit_select_add(i32 %x, i1 %cond, ptr %dst) {
702; X64-LABEL: shl_signbit_select_add:
703; X64:       # %bb.0:
704; X64-NEXT:    movl %edi, %eax
705; X64-NEXT:    shll $4, %eax
706; X64-NEXT:    testb $1, %sil
707; X64-NEXT:    cmovel %edi, %eax
708; X64-NEXT:    addl $123456, %eax # imm = 0x1E240
709; X64-NEXT:    movl %eax, (%rdx)
710; X64-NEXT:    retq
711;
712; X86-LABEL: shl_signbit_select_add:
713; X86:       # %bb.0:
714; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %ecx
715; X86-NEXT:    andb $1, %cl
716; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
717; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
718; X86-NEXT:    negb %cl
719; X86-NEXT:    andb $4, %cl
720; X86-NEXT:    shll %cl, %eax
721; X86-NEXT:    addl $123456, %eax # imm = 0x1E240
722; X86-NEXT:    movl %eax, (%edx)
723; X86-NEXT:    retl
724  %t0 = shl i32 %x, 4
725  %t1 = select i1 %cond, i32 %t0, i32 %x
726  %r = add i32 %t1, 123456
727  store i32 %r, ptr %dst
728  ret i32 %r
729}
730
731define i32 @shl_signbit_select_add_fail(i32 %x, i1 %cond, ptr %dst) {
732; X64-LABEL: shl_signbit_select_add_fail:
733; X64:       # %bb.0:
734; X64-NEXT:    movl %edi, %eax
735; X64-NEXT:    shll $4, %eax
736; X64-NEXT:    testb $1, %sil
737; X64-NEXT:    cmovnel %edi, %eax
738; X64-NEXT:    addl $123456, %eax # imm = 0x1E240
739; X64-NEXT:    movl %eax, (%rdx)
740; X64-NEXT:    retq
741;
742; X86-LABEL: shl_signbit_select_add_fail:
743; X86:       # %bb.0:
744; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
745; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
746; X86-NEXT:    testb $1, {{[0-9]+}}(%esp)
747; X86-NEXT:    jne .LBB25_2
748; X86-NEXT:  # %bb.1:
749; X86-NEXT:    shll $4, %eax
750; X86-NEXT:  .LBB25_2:
751; X86-NEXT:    addl $123456, %eax # imm = 0x1E240
752; X86-NEXT:    movl %eax, (%ecx)
753; X86-NEXT:    retl
754  %t0 = shl i32 %x, 4
755  %t1 = select i1 %cond, i32 %x, i32 %t0
756  %r = add i32 %t1, 123456
757  store i32 %r, ptr %dst
758  ret i32 %r
759}
760
761define i32 @lshr_signbit_select_add(i32 %x, i1 %cond, ptr %dst, i32 %y) {
762; X64-LABEL: lshr_signbit_select_add:
763; X64:       # %bb.0:
764; X64-NEXT:    movl %edi, %eax
765; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
766; X64-NEXT:    shrl %cl, %eax
767; X64-NEXT:    testb $1, %sil
768; X64-NEXT:    cmovel %edi, %eax
769; X64-NEXT:    addl $123456, %eax # imm = 0x1E240
770; X64-NEXT:    movl %eax, (%rdx)
771; X64-NEXT:    retq
772;
773; X86-LABEL: lshr_signbit_select_add:
774; X86:       # %bb.0:
775; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %ecx
776; X86-NEXT:    andb $1, %cl
777; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
778; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
779; X86-NEXT:    negb %cl
780; X86-NEXT:    andb {{[0-9]+}}(%esp), %cl
781; X86-NEXT:    shrl %cl, %eax
782; X86-NEXT:    addl $123456, %eax # imm = 0x1E240
783; X86-NEXT:    movl %eax, (%edx)
784; X86-NEXT:    retl
785  %t0 = lshr i32 %x, %y
786  %t1 = select i1 %cond, i32 %t0, i32 %x
787  %r = add i32 %t1, 123456
788  store i32 %r, ptr %dst
789  ret i32 %r
790}
791
792define i32 @ashr_signbit_select_add(i32 %x, i1 %cond, ptr %dst) {
793; X64-LABEL: ashr_signbit_select_add:
794; X64:       # %bb.0:
795; X64-NEXT:    movl %edi, %eax
796; X64-NEXT:    sarl $4, %eax
797; X64-NEXT:    testb $1, %sil
798; X64-NEXT:    cmovel %edi, %eax
799; X64-NEXT:    addl $123456, %eax # imm = 0x1E240
800; X64-NEXT:    movl %eax, (%rdx)
801; X64-NEXT:    retq
802;
803; X86-LABEL: ashr_signbit_select_add:
804; X86:       # %bb.0:
805; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %ecx
806; X86-NEXT:    andb $1, %cl
807; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
808; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
809; X86-NEXT:    negb %cl
810; X86-NEXT:    andb $4, %cl
811; X86-NEXT:    sarl %cl, %eax
812; X86-NEXT:    addl $123456, %eax # imm = 0x1E240
813; X86-NEXT:    movl %eax, (%edx)
814; X86-NEXT:    retl
815  %t0 = ashr i32 %x, 4
816  %t1 = select i1 %cond, i32 %t0, i32 %x
817  %r = add i32 %t1, 123456
818  store i32 %r, ptr %dst
819  ret i32 %r
820}
821
822define i32 @and_signbit_select_add(i32 %x, i1 %cond, ptr %dst, i32 %y) {
823; X64-LABEL: and_signbit_select_add:
824; X64:       # %bb.0:
825; X64-NEXT:    # kill: def $ecx killed $ecx def $rcx
826; X64-NEXT:    andl %edi, %ecx
827; X64-NEXT:    testb $1, %sil
828; X64-NEXT:    cmovnel %edi, %ecx
829; X64-NEXT:    leal 123456(%rcx), %eax
830; X64-NEXT:    movl %eax, (%rdx)
831; X64-NEXT:    retq
832;
833; X86-LABEL: and_signbit_select_add:
834; X86:       # %bb.0:
835; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
836; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
837; X86-NEXT:    andl $1, %eax
838; X86-NEXT:    negl %eax
839; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
840; X86-NEXT:    andl {{[0-9]+}}(%esp), %eax
841; X86-NEXT:    addl $123456, %eax # imm = 0x1E240
842; X86-NEXT:    movl %eax, (%ecx)
843; X86-NEXT:    retl
844  %t0 = and i32 %x, %y
845  %t1 = select i1 %cond, i32 %x, i32 %t0
846  %r = add i32 %t1, 123456
847  store i32 %r, ptr %dst
848  ret i32 %r
849}
850
851
852define i32 @and_signbit_select_add_fail(i32 %x, i1 %cond, ptr %dst, i32 %y) {
853; X64-LABEL: and_signbit_select_add_fail:
854; X64:       # %bb.0:
855; X64-NEXT:    # kill: def $ecx killed $ecx def $rcx
856; X64-NEXT:    andl %edi, %ecx
857; X64-NEXT:    testb $1, %sil
858; X64-NEXT:    cmovel %edi, %ecx
859; X64-NEXT:    leal 123456(%rcx), %eax
860; X64-NEXT:    movl %eax, (%rdx)
861; X64-NEXT:    retq
862;
863; X86-LABEL: and_signbit_select_add_fail:
864; X86:       # %bb.0:
865; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
866; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
867; X86-NEXT:    testb $1, {{[0-9]+}}(%esp)
868; X86-NEXT:    je .LBB29_2
869; X86-NEXT:  # %bb.1:
870; X86-NEXT:    andl {{[0-9]+}}(%esp), %eax
871; X86-NEXT:  .LBB29_2:
872; X86-NEXT:    addl $123456, %eax # imm = 0x1E240
873; X86-NEXT:    movl %eax, (%ecx)
874; X86-NEXT:    retl
875  %t0 = and i32 %x, %y
876  %t1 = select i1 %cond, i32 %t0, i32 %x
877  %r = add i32 %t1, 123456
878  store i32 %r, ptr %dst
879  ret i32 %r
880}
881
882