xref: /llvm-project/llvm/test/CodeGen/X86/prefetch.ll (revision f0eb5587ceeb641445b64cb264c822b4751de04a)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-- -mattr=+sse | FileCheck %s --check-prefix=X86-SSE
3; RUN: llc < %s -mtriple=i686-- -mattr=+avx | FileCheck %s --check-prefix=X86-SSE
4; RUN: llc < %s -mtriple=i686-- -mattr=+sse,+prfchw | FileCheck %s -check-prefix=X86-PRFCHWSSE
5; RUN: llc < %s -mtriple=i686-- -mattr=+prfchw | FileCheck %s -check-prefix=X86-PRFCHWSSE
6; RUN: llc < %s -mtriple=i686-- -mcpu=slm | FileCheck %s -check-prefix=X86-PRFCHWSSE
7; RUN: llc < %s -mtriple=i686-- -mcpu=btver2 | FileCheck %s -check-prefix=X86-PRFCHWSSE
8; RUN: llc < %s -mtriple=i686-- -mcpu=btver2 -mattr=-prfchw | FileCheck %s -check-prefix=X86-SSE
9; RUN: llc < %s -mtriple=i686-- -mattr=+prfchw | FileCheck %s -check-prefix=X86-PRFCHWSSE
10
11; Rules:
12; sse provides prefetch0/1/2/nta
13; supporting prefetchw implicitly provides prefetcht0/1/2/nta as well, as we need something to fall back to for the non-write hint.
14
15define void @t(ptr %ptr) nounwind  {
16; X86-SSE-LABEL: t:
17; X86-SSE:       # %bb.0: # %entry
18; X86-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
19; X86-SSE-NEXT:    prefetcht2 (%eax)
20; X86-SSE-NEXT:    prefetcht1 (%eax)
21; X86-SSE-NEXT:    prefetcht0 (%eax)
22; X86-SSE-NEXT:    prefetchnta (%eax)
23; X86-SSE-NEXT:    prefetcht2 (%eax)
24; X86-SSE-NEXT:    prefetcht1 (%eax)
25; X86-SSE-NEXT:    prefetcht0 (%eax)
26; X86-SSE-NEXT:    prefetchnta (%eax)
27; X86-SSE-NEXT:    retl
28;
29; X86-PRFCHWSSE-LABEL: t:
30; X86-PRFCHWSSE:       # %bb.0: # %entry
31; X86-PRFCHWSSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
32; X86-PRFCHWSSE-NEXT:    prefetcht2 (%eax)
33; X86-PRFCHWSSE-NEXT:    prefetcht1 (%eax)
34; X86-PRFCHWSSE-NEXT:    prefetcht0 (%eax)
35; X86-PRFCHWSSE-NEXT:    prefetchnta (%eax)
36; X86-PRFCHWSSE-NEXT:    prefetchw (%eax)
37; X86-PRFCHWSSE-NEXT:    prefetchw (%eax)
38; X86-PRFCHWSSE-NEXT:    prefetchw (%eax)
39; X86-PRFCHWSSE-NEXT:    prefetchw (%eax)
40; X86-PRFCHWSSE-NEXT:    retl
41
42entry:
43  tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 1, i32 1 )
44  tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 2, i32 1 )
45  tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 3, i32 1 )
46  tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 0, i32 1 )
47  tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 1, i32 1 )
48  tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 2, i32 1 )
49  tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 3, i32 1 )
50  tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 0, i32 1 )
51  ret void
52}
53
54declare void @llvm.prefetch(ptr, i32, i32, i32) nounwind
55