1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE 3; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE 4; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX 5; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX 6 7define void @PR72539(<8 x i32> %insertelement){ 8; SSE-LABEL: PR72539: 9; SSE: # %bb.0: 10; SSE-NEXT: xorb $7, 0 11; SSE-NEXT: retq 12; 13; AVX-LABEL: PR72539: 14; AVX: # %bb.0: 15; AVX-NEXT: movzbl {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %eax 16; AVX-NEXT: xorb %al, 0 17; AVX-NEXT: retq 18 %load671 = load i8, ptr addrspace(1) null, align 1 19 %shufflevector = shufflevector <8 x i32> %insertelement, <8 x i32> zeroinitializer, <8 x i32> zeroinitializer 20 %xor68 = xor <8 x i32> %shufflevector, <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 21 %call69 = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %xor68) 22 %trunc70 = trunc i32 %call69 to i8 23 %xor71 = xor i8 %load671, %trunc70 24 store i8 %xor71, ptr addrspace(1) null, align 1 25 ret void 26} 27declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32>) 28