1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s 3 4define <64 x i4> @pr62653(<64 x i4> %a0) nounwind { 5; CHECK-LABEL: pr62653: 6; CHECK: # %bb.0: 7; CHECK-NEXT: movq %rdi, %rax 8; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edi 9; CHECK-NEXT: andl $15, %edi 10; CHECK-NEXT: shll $4, %edi 11; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d 12; CHECK-NEXT: andl $15, %r10d 13; CHECK-NEXT: orq %rdi, %r10 14; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edi 15; CHECK-NEXT: andl $15, %edi 16; CHECK-NEXT: shll $8, %edi 17; CHECK-NEXT: orq %r10, %rdi 18; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d 19; CHECK-NEXT: andl $15, %r10d 20; CHECK-NEXT: shll $12, %r10d 21; CHECK-NEXT: orq %rdi, %r10 22; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edi 23; CHECK-NEXT: andl $15, %edi 24; CHECK-NEXT: shll $16, %edi 25; CHECK-NEXT: orq %r10, %rdi 26; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d 27; CHECK-NEXT: andl $15, %r10d 28; CHECK-NEXT: shll $20, %r10d 29; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d 30; CHECK-NEXT: andl $15, %r11d 31; CHECK-NEXT: shll $24, %r11d 32; CHECK-NEXT: orq %r10, %r11 33; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d 34; CHECK-NEXT: shll $28, %r10d 35; CHECK-NEXT: orq %r11, %r10 36; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d 37; CHECK-NEXT: andl $15, %r11d 38; CHECK-NEXT: shlq $32, %r11 39; CHECK-NEXT: orq %r10, %r11 40; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d 41; CHECK-NEXT: andl $15, %r10d 42; CHECK-NEXT: shlq $36, %r10 43; CHECK-NEXT: orq %r11, %r10 44; CHECK-NEXT: orq %rdi, %r10 45; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edi 46; CHECK-NEXT: andl $15, %edi 47; CHECK-NEXT: shlq $40, %rdi 48; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d 49; CHECK-NEXT: andl $15, %r11d 50; CHECK-NEXT: shlq $44, %r11 51; CHECK-NEXT: orq %rdi, %r11 52; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edi 53; CHECK-NEXT: andl $15, %edi 54; CHECK-NEXT: shlq $48, %rdi 55; CHECK-NEXT: orq %r11, %rdi 56; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d 57; CHECK-NEXT: andl $15, %r11d 58; CHECK-NEXT: shlq $52, %r11 59; CHECK-NEXT: orq %rdi, %r11 60; CHECK-NEXT: orq %r10, %r11 61; CHECK-NEXT: movq %r11, 8(%rax) 62; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edi 63; CHECK-NEXT: andl $15, %edi 64; CHECK-NEXT: shlq $32, %rdi 65; CHECK-NEXT: andl $15, %esi 66; CHECK-NEXT: andl $15, %edx 67; CHECK-NEXT: shll $4, %edx 68; CHECK-NEXT: orl %esi, %edx 69; CHECK-NEXT: andl $15, %ecx 70; CHECK-NEXT: shll $8, %ecx 71; CHECK-NEXT: orl %edx, %ecx 72; CHECK-NEXT: andl $15, %r8d 73; CHECK-NEXT: shll $12, %r8d 74; CHECK-NEXT: orl %ecx, %r8d 75; CHECK-NEXT: andl $15, %r9d 76; CHECK-NEXT: shll $16, %r9d 77; CHECK-NEXT: orl %r8d, %r9d 78; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx 79; CHECK-NEXT: andl $15, %ecx 80; CHECK-NEXT: shll $20, %ecx 81; CHECK-NEXT: orl %r9d, %ecx 82; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edx 83; CHECK-NEXT: andl $15, %edx 84; CHECK-NEXT: shll $24, %edx 85; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %esi 86; CHECK-NEXT: shll $28, %esi 87; CHECK-NEXT: orl %edx, %esi 88; CHECK-NEXT: orl %ecx, %esi 89; CHECK-NEXT: orq %rdi, %rsi 90; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx 91; CHECK-NEXT: andl $15, %ecx 92; CHECK-NEXT: shlq $36, %rcx 93; CHECK-NEXT: orq %rsi, %rcx 94; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edx 95; CHECK-NEXT: andl $15, %edx 96; CHECK-NEXT: shlq $40, %rdx 97; CHECK-NEXT: orq %rcx, %rdx 98; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx 99; CHECK-NEXT: andl $15, %ecx 100; CHECK-NEXT: shlq $44, %rcx 101; CHECK-NEXT: orq %rdx, %rcx 102; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edx 103; CHECK-NEXT: andl $15, %edx 104; CHECK-NEXT: shlq $48, %rdx 105; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %esi 106; CHECK-NEXT: andl $15, %esi 107; CHECK-NEXT: shlq $52, %rsi 108; CHECK-NEXT: orq %rdx, %rsi 109; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %edx 110; CHECK-NEXT: andl $15, %edx 111; CHECK-NEXT: shlq $56, %rdx 112; CHECK-NEXT: orq %rsi, %rdx 113; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %esi 114; CHECK-NEXT: shlq $60, %rsi 115; CHECK-NEXT: orq %rdx, %rsi 116; CHECK-NEXT: orq %rcx, %rsi 117; CHECK-NEXT: movq %rsi, (%rax) 118; CHECK-NEXT: retq 119 %res = shufflevector <64 x i4> %a0, <64 x i4> zeroinitializer, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 64, i32 65, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> 120 ret <64 x i4> %res 121} 122