xref: /llvm-project/llvm/test/CodeGen/X86/pr61038.ll (revision 05ca9ebc0433b4e19fc67c1dd023414bc6357f09)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 | FileCheck %s --check-prefix=CHECK-BMI2
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefix=CHECK-BMI2
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi | FileCheck %s --check-prefix=CHECK-BMI
5
6declare i32 @llvm.cttz.i32(i32, i1 immarg)
7define void @test_61038(ptr %tmp_buffer) {
8; CHECK-BMI2-LABEL: test_61038:
9; CHECK-BMI2:       # %bb.0: # %entry
10; CHECK-BMI2-NEXT:    tzcntl %eax, %eax
11; CHECK-BMI2-NEXT:    movabsq $8589934591, %rcx # imm = 0x1FFFFFFFF
12; CHECK-BMI2-NEXT:    movq %rcx, %rdx
13; CHECK-BMI2-NEXT:    btcq %rax, %rdx
14; CHECK-BMI2-NEXT:    xorl %eax, %eax
15; CHECK-BMI2-NEXT:    cmpq $64, %rdx
16; CHECK-BMI2-NEXT:    shrxq %rdx, %rcx, %rcx
17; CHECK-BMI2-NEXT:    cmovael %eax, %ecx
18; CHECK-BMI2-NEXT:    movl %ecx, (%rdi)
19; CHECK-BMI2-NEXT:    retq
20;
21; CHECK-BMI-LABEL: test_61038:
22; CHECK-BMI:       # %bb.0: # %entry
23; CHECK-BMI-NEXT:    tzcntl %eax, %eax
24; CHECK-BMI-NEXT:    movabsq $8589934591, %rdx # imm = 0x1FFFFFFFF
25; CHECK-BMI-NEXT:    movq %rdx, %rcx
26; CHECK-BMI-NEXT:    btcq %rax, %rcx
27; CHECK-BMI-NEXT:    shrq %cl, %rdx
28; CHECK-BMI-NEXT:    xorl %eax, %eax
29; CHECK-BMI-NEXT:    cmpq $64, %rcx
30; CHECK-BMI-NEXT:    cmovael %eax, %edx
31; CHECK-BMI-NEXT:    movl %edx, (%rdi)
32; CHECK-BMI-NEXT:    retq
33entry:
34  %0 = tail call i32 @llvm.cttz.i32(i32 poison, i1 false)
35  %1 = zext i32 %0 to i64
36  %2 = shl nuw nsw i64 1, %1
37  %3 = xor i64 %2, 8589934591
38  %4 = icmp ugt i64 %3, 63
39  %x11.op.i = lshr i64 8589934591, %3
40  %5 = trunc i64 %x11.op.i to i32
41  %6 = select i1 %4, i32 0, i32 %5
42  store i32 %6, ptr %tmp_buffer, align 4
43  ret void
44}
45