1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx512f | FileCheck %s 3 4; The alignment of 16 causes type legalization to split this as 3 loads, 5; v16f32, v4f32, and v4f32. This loads 24 elements, but the load is aligned 6; to 16 bytes so this i safe. There was an issue with type legalization building 7; the proper concat_vectors for this because the two v4f32s don't add up to 8; v16f32 and require padding. 9 10define <23 x float> @load23(ptr %p) { 11; CHECK-LABEL: load23: 12; CHECK: # %bb.0: 13; CHECK-NEXT: movq %rdi, %rax 14; CHECK-NEXT: vmovups (%rsi), %zmm0 15; CHECK-NEXT: vmovaps 64(%rsi), %xmm1 16; CHECK-NEXT: vmovdqa 80(%rsi), %xmm2 17; CHECK-NEXT: vextractps $2, %xmm2, 88(%rdi) 18; CHECK-NEXT: vmovq %xmm2, 80(%rdi) 19; CHECK-NEXT: vmovaps %xmm1, 64(%rdi) 20; CHECK-NEXT: vmovaps %zmm0, (%rdi) 21; CHECK-NEXT: vzeroupper 22; CHECK-NEXT: retq 23 %t0 = load <23 x float>, ptr %p, align 16 24 ret <23 x float> %t0 25} 26 27; Same test as above with minimal alignment just to demonstrate the different 28; codegen. 29define <23 x float> @load23_align_1(ptr %p) { 30; CHECK-LABEL: load23_align_1: 31; CHECK: # %bb.0: 32; CHECK-NEXT: movq %rdi, %rax 33; CHECK-NEXT: vmovups (%rsi), %zmm0 34; CHECK-NEXT: vmovups 64(%rsi), %xmm1 35; CHECK-NEXT: movq 80(%rsi), %rcx 36; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero 37; CHECK-NEXT: vmovss %xmm2, 88(%rdi) 38; CHECK-NEXT: movq %rcx, 80(%rdi) 39; CHECK-NEXT: vmovaps %xmm1, 64(%rdi) 40; CHECK-NEXT: vmovaps %zmm0, (%rdi) 41; CHECK-NEXT: vzeroupper 42; CHECK-NEXT: retq 43 %t0 = load <23 x float>, ptr %p, align 1 44 ret <23 x float> %t0 45} 46