xref: /llvm-project/llvm/test/CodeGen/X86/pr43509.ll (revision 30b63def5096cbee448176cc82ca5f6c995f16c4)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s
3
4define <8 x i8> @foo(<8 x float> %arg) {
5; CHECK-LABEL: foo:
6; CHECK:       # %bb.0: # %bb
7; CHECK-NEXT:    vxorps %xmm1, %xmm1, %xmm1
8; CHECK-NEXT:    vcmpltps %ymm1, %ymm0, %k1
9; CHECK-NEXT:    vcmpgtps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1 {%k1}
10; CHECK-NEXT:    vmovdqu8 {{.*#+}} xmm0 {%k1} {z} = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
11; CHECK-NEXT:    vzeroupper
12; CHECK-NEXT:    retq
13bb:
14  %tmp = xor <8 x i8> zeroinitializer, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
15  %tmp1 = fcmp reassoc nsz contract ogt <8 x float> %arg, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
16  %tmp2 = zext <8 x i1> %tmp1 to <8 x i8>
17  %tmp3 = and <8 x i8> %tmp, %tmp2
18  %tmp4 = fcmp reassoc nsz contract ogt <8 x float> zeroinitializer, %arg
19  %tmp5 = or <8 x i1> zeroinitializer, %tmp4
20  %tmp6 = zext <8 x i1> %tmp5 to <8 x i8>
21  %tmp7 = and <8 x i8> %tmp3, %tmp6
22  ret <8 x i8> %tmp7
23}
24