xref: /llvm-project/llvm/test/CodeGen/X86/pr42998.ll (revision 6599961c17073204ac868958e632cf4d92353cbe)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s --check-prefixes=CHECK,FAST-INCDEC
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=goldmont | FileCheck %s --check-prefixes=CHECK,SLOW-INCDEC
4
5define i64 @imm1_Oz(i32 %x, i32 %y) minsize nounwind {
6; CHECK-LABEL: imm1_Oz:
7; CHECK:       # %bb.0:
8; CHECK:         incl %edi
9; CHECK-NEXT:    leal 1(%rsi), %eax
10; CHECK-NEXT:    addq %rdi, %rax
11; CHECK-NEXT:    retq
12  %x1 = add i32 %x, 1
13  %y1 = add i32 %y, 1
14  %x1z = zext i32 %x1 to i64
15  %y1z = zext i32 %y1 to i64
16  %r = add i64 %x1z, %y1z
17  ret i64 %r
18}
19
20define i64 @imm1_Os(i32 %x, i32 %y) optsize nounwind {
21; CHECK-LABEL: imm1_Os:
22; CHECK:       # %bb.0:
23; CHECK:         incl %edi
24; CHECK-NEXT:    leal 1(%rsi), %eax
25; CHECK-NEXT:    addq %rdi, %rax
26; CHECK-NEXT:    retq
27  %x1 = add i32 %x, 1
28  %y1 = add i32 %y, 1
29  %x1z = zext i32 %x1 to i64
30  %y1z = zext i32 %y1 to i64
31  %r = add i64 %x1z, %y1z
32  ret i64 %r
33}
34
35define i64 @imm1_O2(i32 %x, i32 %y) nounwind {
36; FAST-INCDEC-LABEL: imm1_O2:
37; FAST-INCDEC:       # %bb.0:
38; FAST-INCDEC-NEXT:    # kill: def $esi killed $esi def $rsi
39; FAST-INCDEC-NEXT:    # kill: def $edi killed $edi def $rdi
40; FAST-INCDEC-NEXT:    incl %edi
41; FAST-INCDEC-NEXT:    leal 1(%rsi), %eax
42; FAST-INCDEC-NEXT:    addq %rdi, %rax
43; FAST-INCDEC-NEXT:    retq
44;
45; SLOW-INCDEC-LABEL: imm1_O2:
46; SLOW-INCDEC:       # %bb.0:
47; SLOW-INCDEC-NEXT:    # kill: def $edi killed $edi def $rdi
48; SLOW-INCDEC-NEXT:    # kill: def $esi killed $esi def $rsi
49; SLOW-INCDEC-NEXT:    addl $1, %edi
50; SLOW-INCDEC-NEXT:    leal 1(%rsi), %eax
51; SLOW-INCDEC-NEXT:    addq %rdi, %rax
52; SLOW-INCDEC-NEXT:    retq
53  %x1 = add i32 %x, 1
54  %y1 = add i32 %y, 1
55  %x1z = zext i32 %x1 to i64
56  %y1z = zext i32 %y1 to i64
57  %r = add i64 %x1z, %y1z
58  ret i64 %r
59}
60