xref: /llvm-project/llvm/test/CodeGen/X86/pr40994.ll (revision 2f448bf509432c1a19ec46ab8cbc7353c03c6280) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.2 | FileCheck %s
3
4define <8 x i8> @foo(<16 x i8> %a) {
5; CHECK-LABEL: foo:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    pextrb $0, %xmm0, -{{[0-9]+}}(%rsp)
8; CHECK-NEXT:    pextrb $2, %xmm0, -{{[0-9]+}}(%rsp)
9; CHECK-NEXT:    pextrb $4, %xmm0, -{{[0-9]+}}(%rsp)
10; CHECK-NEXT:    pextrb $6, %xmm0, -{{[0-9]+}}(%rsp)
11; CHECK-NEXT:    pextrb $8, %xmm0, -{{[0-9]+}}(%rsp)
12; CHECK-NEXT:    pextrb $10, %xmm0, -{{[0-9]+}}(%rsp)
13; CHECK-NEXT:    pextrb $12, %xmm0, -{{[0-9]+}}(%rsp)
14; CHECK-NEXT:    pextrb $14, %xmm0, -{{[0-9]+}}(%rsp)
15; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
16; CHECK-NEXT:    retq
17  %v = alloca i8, i32 8, align 16
18  call void @llvm.masked.compressstore.v16i8(<16 x i8> %a, ptr %v, <16 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>)
19  %out = load <8 x i8>, ptr %v
20  ret <8 x i8> %out
21}
22declare void @llvm.masked.compressstore.v16i8(<16 x i8>, ptr, <16 x i1>) #0
23