1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=skylake | FileCheck %s --check-prefix=X86 3; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=skx | FileCheck %s --check-prefix=X86 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake | FileCheck %s --check-prefix=X64 5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s --check-prefix=X64 6 7define void @fetch_r16g16_snorm_unorm8(ptr, ptr, i32, i32, ptr) nounwind { 8; X86-LABEL: fetch_r16g16_snorm_unorm8: 9; X86: # %bb.0: # %entry 10; X86-NEXT: movl {{[0-9]+}}(%esp), %eax 11; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx 12; X86-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero 13; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1 14; X86-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 15; X86-NEXT: vpsrlw $7, %xmm0, %xmm0 16; X86-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2],zero,xmm0[u,u,u,u,u,u,u,u,u,u,u,u,u] 17; X86-NEXT: vmovd %xmm0, %ecx 18; X86-NEXT: orl $-16777216, %ecx # imm = 0xFF000000 19; X86-NEXT: movl %ecx, (%eax) 20; X86-NEXT: retl 21; 22; X64-LABEL: fetch_r16g16_snorm_unorm8: 23; X64: # %bb.0: # %entry 24; X64-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero 25; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1 26; X64-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 27; X64-NEXT: vpsrlw $7, %xmm0, %xmm0 28; X64-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2],zero,xmm0[u,u,u,u,u,u,u,u,u,u,u,u,u] 29; X64-NEXT: vmovd %xmm0, %eax 30; X64-NEXT: orl $-16777216, %eax # imm = 0xFF000000 31; X64-NEXT: movl %eax, (%rdi) 32; X64-NEXT: retq 33entry: 34 %5 = load <2 x i16>, ptr %1, align 2 35 %6 = shufflevector <2 x i16> %5, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> 36 %7 = icmp sgt <4 x i16> %6, zeroinitializer 37 %8 = select <4 x i1> %7, <4 x i16> %6, <4 x i16> zeroinitializer 38 %9 = lshr <4 x i16> %8, <i16 7, i16 7, i16 7, i16 7> 39 %10 = shufflevector <4 x i16> %9, <4 x i16> undef, <2 x i32> <i32 0, i32 1> 40 %11 = shufflevector <4 x i16> %9, <4 x i16> undef, <2 x i32> <i32 2, i32 3> 41 %12 = bitcast <2 x i16> %10 to <4 x i8> 42 %13 = bitcast <2 x i16> %11 to <4 x i8> 43 %14 = shufflevector <4 x i8> %12, <4 x i8> %13, <4 x i32> <i32 0, i32 2, i32 4, i32 6> 44 %15 = bitcast <4 x i8> %14 to i32 45 %16 = and i32 %15, 65535 46 %17 = or i32 %16, -16777216 47 store i32 %17, ptr %0, align 4 48 ret void 49} 50