xref: /llvm-project/llvm/test/CodeGen/X86/pr34855.ll (revision 2f448bf509432c1a19ec46ab8cbc7353c03c6280)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86
3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
4
5define void @PR34855(ptr%p0, ptr%p1, ptr%p2) {
6; X86-LABEL: PR34855:
7; X86:       # %bb.0:
8; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
9; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
10; X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
11; X86-NEXT:    movsd %xmm0, (%eax)
12; X86-NEXT:    retl
13;
14; X64-LABEL: PR34855:
15; X64:       # %bb.0:
16; X64-NEXT:    movq (%rdi), %rax
17; X64-NEXT:    movq %rax, (%rdx)
18; X64-NEXT:    retq
19  %tmp = load <2 x i32>, ptr %p0, align 8
20  %tmp1 = load <2 x i32>, ptr %p1, align 8
21  %mul = mul <2 x i32> zeroinitializer, %tmp1
22  %mul1 = mul <2 x i32> <i32 -8190, i32 -8190>, %mul
23  %mul2 = mul <2 x i32> <i32 3, i32 3>, %mul1
24  %shr = ashr <2 x i32> %tmp, %mul2
25  store <2 x i32> %shr, ptr %p2, align 8
26  ret void
27}
28