xref: /llvm-project/llvm/test/CodeGen/X86/pr34137.ll (revision 2f448bf509432c1a19ec46ab8cbc7353c03c6280)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
3
4@var_3 = external dso_local global i16, align 2
5@var_13 = external dso_local global i16, align 2
6@var_212 = external dso_local global i64, align 8
7
8define void @pr34127() {
9; CHECK-LABEL: pr34127:
10; CHECK:       # %bb.0: # %entry
11; CHECK-NEXT:    movzwl var_13(%rip), %eax
12; CHECK-NEXT:    movzwl var_3(%rip), %ecx
13; CHECK-NEXT:    andw %ax, %cx
14; CHECK-NEXT:    movzwl %cx, %ecx
15; CHECK-NEXT:    movl %ecx, -{{[0-9]+}}(%rsp)
16; CHECK-NEXT:    movzwl var_3(%rip), %ecx
17; CHECK-NEXT:    xorl %edx, %edx
18; CHECK-NEXT:    testl %eax, %ecx
19; CHECK-NEXT:    sete %dl
20; CHECK-NEXT:    andl %ecx, %edx
21; CHECK-NEXT:    movq %rdx, var_212(%rip)
22; CHECK-NEXT:    movw $0, (%rax)
23; CHECK-NEXT:    retq
24entry:
25  %a = alloca i32, align 4
26  %0 = load i16, ptr @var_3, align 2
27  %conv = zext i16 %0 to i32
28  %1 = load i16, ptr @var_3, align 2
29  %conv1 = zext i16 %1 to i32
30  %2 = load i16, ptr @var_13, align 2
31  %conv2 = zext i16 %2 to i32
32  %and = and i32 %conv1, %conv2
33  %and3 = and i32 %conv, %and
34  store i32 %and3, ptr %a, align 4
35  %3 = load i16, ptr @var_3, align 2
36  %conv4 = zext i16 %3 to i32
37  %4 = load i16, ptr @var_3, align 2
38  %conv5 = zext i16 %4 to i32
39  %5 = load i16, ptr @var_13, align 2
40  %conv6 = zext i16 %5 to i32
41  %and7 = and i32 %conv5, %conv6
42  %and8 = and i32 %conv4, %and7
43  %tobool = icmp ne i32 %and8, 0
44  %lnot = xor i1 %tobool, true
45  %conv9 = zext i1 %lnot to i32
46  %6 = load i16, ptr @var_3, align 2
47  %conv10 = zext i16 %6 to i32
48  %and11 = and i32 %conv9, %conv10
49  %conv12 = sext i32 %and11 to i64
50  store i64 %conv12, ptr @var_212, align 8
51  %conv14 = zext i1 undef to i16
52  store i16 %conv14, ptr undef, align 2
53  ret void
54}
55