xref: /llvm-project/llvm/test/CodeGen/X86/pr18014.ll (revision 2f448bf509432c1a19ec46ab8cbc7353c03c6280)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s
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4; Ensure PSRAD is generated as the condition is consumed by both PADD and
5; BLENDVPS. PADD requires all bits setting properly.
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7define <4 x i32> @foo(ptr %p, <4 x i1> %cond, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
8; CHECK-LABEL: foo:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    pslld $31, %xmm0
11; CHECK-NEXT:    movdqa %xmm0, %xmm3
12; CHECK-NEXT:    psrad $31, %xmm3
13; CHECK-NEXT:    paddd %xmm1, %xmm3
14; CHECK-NEXT:    blendvps %xmm0, %xmm1, %xmm2
15; CHECK-NEXT:    movaps %xmm2, (%rdi)
16; CHECK-NEXT:    movdqa %xmm3, %xmm0
17; CHECK-NEXT:    retq
18  %sext_cond = sext <4 x i1> %cond to <4 x i32>
19  %t1 = add <4 x i32> %v1, %sext_cond
20  %t2 = select <4 x i1> %cond, <4 x i32> %v1, <4 x i32> %v2
21  store <4 x i32> %t2, ptr %p
22  ret <4 x i32> %t1
23}
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