1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=corei7-avx -enable-misched=false | FileCheck %s 3 4define i64 @main(i1 %tobool1) nounwind { 5; CHECK-LABEL: main: 6; CHECK: # %bb.0: # %entry 7; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax 8; CHECK-NEXT: andl $1, %eax 9; CHECK-NEXT: decl %eax 10; CHECK-NEXT: orl $-12, %eax 11; CHECK-NEXT: xorl %ecx, %ecx 12; CHECK-NEXT: movl %eax, %edx 13; CHECK-NEXT: addl $-1, %edx 14; CHECK-NEXT: movl $0, %edx 15; CHECK-NEXT: adcl $-2, %edx 16; CHECK-NEXT: cmovsl %ecx, %eax 17; CHECK-NEXT: xorl %edx, %edx 18; CHECK-NEXT: retl 19entry: 20 %0 = zext i1 %tobool1 to i32 21 %. = xor i32 %0, 1 22 %.21 = select i1 %tobool1, i32 -12, i32 -1 23 %conv = sext i32 %.21 to i64 24 %1 = add i64 %conv, -1 25 %cmp10 = icmp slt i64 %1, 0 26 %sub17 = select i1 %cmp10, i64 0, i64 %conv 27 ret i64 %sub17 28} 29