xref: /llvm-project/llvm/test/CodeGen/X86/peephole-nofold-tpoff-x86.mir (revision d68ba43ad24791181280fdb0f34b6be380db7a32)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -run-pass=peephole-opt -mtriple=i386-- %s -o - | FileCheck %s
3
4# Linkers may change `addq xx@GOTNTPOFF, %reg` to `leaq OFFSET(%reg), %reg`,
5# so we must not depend upon the EFLAGS output. Verify that the TEST
6# instruction won't be folded into the ADD.
7
8# NOTE: the IR will no longer actually produce the input MIR after
9# llvm.threadlocal.address intrinsic is annotated as having a nonnull
10# result.
11
12# NOTE2: the foo_nopic MIR was produced from IR with --relocation-model=static
13# while foo_pic's MIR was produced with --relocation-model=pic.
14
15--- |
16  target datalayout = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-f64:32:64-f80:32-n8:16:32-S128"
17  target triple = "i386-unknown-linux-gnu"
18
19  @x = external thread_local(initialexec) global i32, align 4
20
21  define i32 @foo_nopic() {
22    %1 = tail call ptr @llvm.threadlocal.address.p0(ptr nonnull @x)
23    %cmp = icmp eq ptr %1, null
24    %zext = zext i1 %cmp to i32
25    ret i32 %zext
26  }
27
28  define i32 @foo_pic() {
29    %1 = tail call ptr @llvm.threadlocal.address.p0(ptr nonnull @x)
30    %cmp = icmp eq ptr %1, null
31    %zext = zext i1 %cmp to i32
32    ret i32 %zext
33  }
34
35  ; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn
36  declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) #0
37
38  attributes #0 = { nocallback nofree nosync nounwind readnone speculatable willreturn }
39
40...
41---
42name:            foo_nopic
43alignment:       16
44tracksRegLiveness: true
45registers:
46  - { id: 0, class: gr32 }
47  - { id: 1, class: gr32 }
48  - { id: 2, class: gr8 }
49  - { id: 3, class: gr32 }
50frameInfo:
51  maxAlignment:    1
52machineFunctionInfo: {}
53body:             |
54  bb.0 (%ir-block.0):
55    ; CHECK-LABEL: name: foo_nopic
56    ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm $noreg, 1, $noreg, 0, $gs :: (load (s32) from `ptr addrspace(256) null`, addrspace 256)
57    ; CHECK-NEXT: [[ADD32rm:%[0-9]+]]:gr32 = ADD32rm [[MOV32rm]], $noreg, 1, $noreg, target-flags(x86-indntpoff) @x, $noreg, implicit-def dead $eflags :: (load (s32) from got)
58    ; CHECK-NEXT: TEST32rr [[ADD32rm]], [[ADD32rm]], implicit-def $eflags
59    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
60    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr]]
61    ; CHECK-NEXT: $eax = COPY [[MOVZX32rr8_]]
62    ; CHECK-NEXT: RET 0, $eax
63    %0:gr32 = MOV32rm $noreg, 1, $noreg, 0, $gs :: (load (s32) from `ptr addrspace(256) null`, addrspace 256)
64    %1:gr32 = ADD32rm %0, $noreg, 1, $noreg, target-flags(x86-indntpoff) @x, $noreg, implicit-def dead $eflags :: (load (s32) from got)
65    TEST32rr %1, %1, implicit-def $eflags
66    %2:gr8 = SETCCr 4, implicit $eflags
67    %3:gr32 = MOVZX32rr8 killed %2
68    $eax = COPY %3
69    RET 0, $eax
70
71...
72---
73name:            foo_pic
74alignment:       16
75tracksRegLiveness: true
76registers:
77  - { id: 0, class: gr32_nosp }
78  - { id: 1, class: gr32 }
79  - { id: 2, class: gr32 }
80  - { id: 3, class: gr8 }
81  - { id: 4, class: gr32 }
82  - { id: 5, class: gr32 }
83frameInfo:
84  maxAlignment:    1
85machineFunctionInfo: {}
86body:             |
87  bb.0 (%ir-block.0):
88    ; CHECK-LABEL: name: foo_pic
89    ; CHECK: [[MOVPC32r:%[0-9]+]]:gr32 = MOVPC32r 0, implicit $esp, implicit $ssp
90    ; CHECK-NEXT: [[ADD32ri:%[0-9]+]]:gr32_nosp = ADD32ri [[MOVPC32r]], target-flags(x86-got-absolute-address) &_GLOBAL_OFFSET_TABLE_, implicit-def $eflags
91    ; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm $noreg, 1, $noreg, 0, $gs :: (load (s32) from `ptr addrspace(256) null`, addrspace 256)
92    ; CHECK-NEXT: [[ADD32rm:%[0-9]+]]:gr32 = ADD32rm [[MOV32rm]], [[ADD32ri]], 1, $noreg, target-flags(x86-gotntpoff) @x, $noreg, implicit-def dead $eflags :: (load (s32) from got)
93    ; CHECK-NEXT: TEST32rr [[ADD32rm]], [[ADD32rm]], implicit-def $eflags
94    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
95    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr]]
96    ; CHECK-NEXT: $eax = COPY [[MOVZX32rr8_]]
97    ; CHECK-NEXT: RET 0, $eax
98    %5:gr32 = MOVPC32r 0, implicit $esp, implicit $ssp
99    %0:gr32_nosp = ADD32ri %5, target-flags(x86-got-absolute-address) &_GLOBAL_OFFSET_TABLE_, implicit-def $eflags
100    %1:gr32 = MOV32rm $noreg, 1, $noreg, 0, $gs :: (load (s32) from `ptr addrspace(256) null`, addrspace 256)
101    %2:gr32 = ADD32rm %1, %0, 1, $noreg, target-flags(x86-gotntpoff) @x, $noreg, implicit-def dead $eflags :: (load (s32) from got)
102    TEST32rr %2, %2, implicit-def $eflags
103    %3:gr8 = SETCCr 4, implicit $eflags
104    %4:gr32 = MOVZX32rr8 killed %3
105    $eax = COPY %4
106    RET 0, $eax
107...
108