xref: /llvm-project/llvm/test/CodeGen/X86/no-sse2-avg.ll (revision 2d0f20cc043458c945e4959c5b130c07a7f5b8b5)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; REQUIRES: asserts
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s
4
5define <16 x i8> @PR27973() {
6; CHECK-LABEL: PR27973:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    movq %rdi, %rax
9; CHECK-NEXT:    movq $0, 8(%rdi)
10; CHECK-NEXT:    movq $0, (%rdi)
11; CHECK-NEXT:    retq
12  %t0 = zext <16 x i8> zeroinitializer to <16 x i32>
13  %t1 = add nuw nsw <16 x i32> %t0, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
14  %t2 = lshr <16 x i32> %t1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
15  %t3 = trunc <16 x i32> %t2 to <16 x i8>
16  ret <16 x i8> %t3
17}
18