xref: /llvm-project/llvm/test/CodeGen/X86/neg-shl-add.ll (revision 584ed8822631481ced8d3574cc1fed1585aed77d)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s
3; These sequences don't need neg instructions; they can be done with
4; a single shift and sub each.
5
6define i64 @foo(i64 %x, i64 %y, i64 %n) nounwind {
7; CHECK-LABEL: foo:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    movq %rdx, %rcx
10; CHECK-NEXT:    movq %rdi, %rax
11; CHECK-NEXT:    # kill: def $cl killed $cl killed $rcx
12; CHECK-NEXT:    shlq %cl, %rsi
13; CHECK-NEXT:    subq %rsi, %rax
14; CHECK-NEXT:    retq
15  %a = sub i64 0, %y
16  %b = shl i64 %a, %n
17  %c = add i64 %b, %x
18  ret i64 %c
19}
20define i64 @boo(i64 %x, i64 %y, i64 %n) nounwind {
21; CHECK-LABEL: boo:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    movq %rdx, %rcx
24; CHECK-NEXT:    movq %rdi, %rax
25; CHECK-NEXT:    # kill: def $cl killed $cl killed $rcx
26; CHECK-NEXT:    shlq %cl, %rsi
27; CHECK-NEXT:    subq %rsi, %rax
28; CHECK-NEXT:    retq
29  %a = sub i64 0, %y
30  %b = shl i64 %a, %n
31  %c = add i64 %x, %b
32  ret i64 %c
33}
34