xref: /llvm-project/llvm/test/CodeGen/X86/mxcsr-reg-usage.ll (revision b7e4fba6e5dcae5ff51f8eced21470a1b3ccd895) 
1; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+mmx,+fma,+f16c,+avx512f -stop-after finalize-isel -o - %s | FileCheck %s
2; This test ensures that the MXCSR is implicitly used by MMX FP instructions.
3
4define <1 x i64> @mxcsr_mmx(<4 x float> %a0) {
5; CHECK: MMX_CVTPS2PIrr %{{[0-9]}}, implicit $mxcsr
6; CHECK: MMX_CVTPI2PSrr %{{[0-9]}}, killed %{{[0-9]}}, implicit $mxcsr
7; CHECK: MMX_CVTTPS2PIrr killed %{{[0-9]}}, implicit $mxcsr
8; CHECK: MMX_CVTPI2PDrr killed %{{[0-9]$}}
9; CHECK: MMX_CVTPD2PIrr killed %{{[0-9]}}, implicit $mxcsr
10  %1 = call <1 x i64> @llvm.x86.sse.cvtps2pi(<4 x float> %a0)
11  %2 = call <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> %a0, <1 x i64> %1)
12  %3 = call <1 x i64> @llvm.x86.sse.cvttps2pi(<4 x float> %2)
13  %4 = call <2 x double> @llvm.x86.sse.cvtpi2pd(<1 x i64> %3)
14  %5 = call <1 x i64> @llvm.x86.sse.cvtpd2pi(<2 x double> %4)
15  ret <1 x i64> %5
16}
17
18define half @mxcsr_f16c(float %a) {
19; CHECK: VCVTPS2PH{{.*}}mxcsr
20  %res = fptrunc float %a to half
21  ret half %res
22}
23
24define <4 x float> @mxcsr_fma_ss(<4 x float> %a, <4 x float> %b) {
25; CHECK: VFMADD{{.*}}mxcsr
26  %res = call <4 x float> @llvm.x86.fma.vfmadd.ss(<4 x float> %b, <4 x float> %a, <4 x float>
27%a)
28  ret <4 x float> %res
29}
30
31define <4 x float> @mxcsr_fma_ps(<4 x float> %a, <4 x float> %b) {
32; CHECK: VFMADD{{.*}}mxcsr
33  %res = call <4 x float> @llvm.x86.fma.vfmadd.ps(<4 x float> %b, <4 x float> %a, <4 x float>
34%a)
35  ret <4 x float> %res
36}
37
38define <8 x double> @mxcsr_fma_sae(<8 x double> %a, <8 x double> %b, <8 x double> %c) {
39; CHECK: VFMADD{{.*}}mxcsr
40  %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a, <8 x double> %b, <8 x double> %c, i8 -1, i32 10)
41  ret <8 x double> %res
42}
43
44declare <1 x i64> @llvm.x86.sse.cvtps2pi(<4 x float>)
45declare<4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float>, <1 x i64>)
46declare <1 x i64> @llvm.x86.sse.cvttps2pi(<4 x float>)
47declare <2 x double> @llvm.x86.sse.cvtpi2pd(<1 x i64>)
48declare <1 x i64> @llvm.x86.sse.cvtpd2pi(<2 x double>)
49declare <4 x float> @llvm.x86.fma.vfmadd.ss(<4 x float>, <4 x float>, <4 x float>)
50declare <4 x float> @llvm.x86.fma.vfmadd.ps(<4 x float>, <4 x float>, <4 x float>)
51declare <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)
52