xref: /llvm-project/llvm/test/CodeGen/X86/ms-inline-asm-variables-x86-1-reg.ll (revision 2f448bf509432c1a19ec46ab8cbc7353c03c6280)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=i386-unknown-unknown %s -o - | FileCheck --check-prefix=X86 %s
3; RUN: llc -mtriple=i386-unknown-unknown -relocation-model=pic %s -o -| FileCheck --check-prefix=X86PIC %s
4
5; Tests come from clang/test/CodeGen/ms-inline-asm-variables.c
6;
7; int gVar;
8; void t1() {
9;  __asm add eax, dword ptr gVar[eax]
10;  __asm add dword ptr [eax+gVar], eax
11;  __asm add ebx, dword ptr gVar[271 - 82 + 81 + ebx]
12;  __asm add dword ptr [ebx + gVar + 828], ebx
13;  gVar = 3;
14; }
15;
16; void t2(void) {
17;  int lVar;
18;  __asm mov eax, dword ptr lVar[eax]
19;  __asm mov dword ptr [eax+lVar], eax
20;  __asm mov ebx, dword ptr lVar[271 - 82 + 81 + ebx]
21;  __asm mov dword ptr [ebx + lVar + 828], ebx
22;  __asm mov 5 + 8 + 13 + 21[lVar + ebx], eax
23;  lVar = 2;
24; }
25
26@gVar = global i32 0, align 4
27
28; Function Attrs: noinline nounwind optnone uwtable
29define void @t1() #0 {
30; X86-LABEL: t1:
31; X86:       # %bb.0: # %entry
32; X86-NEXT:    pushl %ebp
33; X86-NEXT:    .cfi_def_cfa_offset 8
34; X86-NEXT:    .cfi_offset %ebp, -8
35; X86-NEXT:    movl %esp, %ebp
36; X86-NEXT:    .cfi_def_cfa_register %ebp
37; X86-NEXT:    pushl %ebx
38; X86-NEXT:    .cfi_offset %ebx, -12
39; X86-NEXT:    #APP
40; X86-EMPTY:
41; X86-NEXT:    addl gVar(%eax), %eax
42; X86-NEXT:    addl %eax, gVar(%eax)
43; X86-NEXT:    addl gVar+270(%ebx), %ebx
44; X86-NEXT:    addl %ebx, gVar+828(%ebx)
45; X86-EMPTY:
46; X86-NEXT:    #NO_APP
47; X86-NEXT:    movl $3, gVar
48; X86-NEXT:    popl %ebx
49; X86-NEXT:    popl %ebp
50; X86-NEXT:    .cfi_def_cfa %esp, 4
51; X86-NEXT:    retl
52;
53; X86PIC-LABEL: t1:
54; X86PIC:       # %bb.0: # %entry
55; X86PIC-NEXT:    pushl %ebp
56; X86PIC-NEXT:    .cfi_def_cfa_offset 8
57; X86PIC-NEXT:    .cfi_offset %ebp, -8
58; X86PIC-NEXT:    movl %esp, %ebp
59; X86PIC-NEXT:    .cfi_def_cfa_register %ebp
60; X86PIC-NEXT:    pushl %ebx
61; X86PIC-NEXT:    .cfi_offset %ebx, -12
62; X86PIC-NEXT:    calll .L0$pb
63; X86PIC-NEXT:  .L0$pb:
64; X86PIC-NEXT:    popl %ecx
65; X86PIC-NEXT:  .Ltmp0:
66; X86PIC-NEXT:    addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp0-.L0$pb), %ecx
67; X86PIC-NEXT:    movl gVar@GOT(%ecx), %edx
68; X86PIC-NEXT:    #APP
69; X86PIC-EMPTY:
70; X86PIC-NEXT:    addl (%edx,%eax), %eax
71; X86PIC-NEXT:    addl %eax, (%edx,%eax)
72; X86PIC-NEXT:    addl 270(%edx,%ebx), %ebx
73; X86PIC-NEXT:    addl %ebx, 828(%edx,%ebx)
74; X86PIC-EMPTY:
75; X86PIC-NEXT:    #NO_APP
76; X86PIC-NEXT:    movl gVar@GOT(%ecx), %eax
77; X86PIC-NEXT:    movl $3, (%eax)
78; X86PIC-NEXT:    popl %ebx
79; X86PIC-NEXT:    popl %ebp
80; X86PIC-NEXT:    .cfi_def_cfa %esp, 4
81; X86PIC-NEXT:    retl
82entry:
83  call void asm sideeffect inteldialect "add eax, dword ptr $2[eax]\0A\09add dword ptr $0[eax], eax\0A\09add ebx, dword ptr $3[ebx + $$270]\0A\09add dword ptr $1[ebx + $$828], ebx", "=*m,=*m,*m,*m,~{eax},~{ebx},~{flags},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) @gVar, ptr elementtype(i32) @gVar, ptr elementtype(i32) @gVar, ptr elementtype(i32) @gVar)
84  store i32 3, ptr @gVar, align 4
85  ret void
86}
87
88; Function Attrs: noinline nounwind optnone uwtable
89define void @t2() #0 {
90; X86-LABEL: t2:
91; X86:       # %bb.0: # %entry
92; X86-NEXT:    pushl %ebp
93; X86-NEXT:    .cfi_def_cfa_offset 8
94; X86-NEXT:    .cfi_offset %ebp, -8
95; X86-NEXT:    movl %esp, %ebp
96; X86-NEXT:    .cfi_def_cfa_register %ebp
97; X86-NEXT:    pushl %ebx
98; X86-NEXT:    pushl %eax
99; X86-NEXT:    .cfi_offset %ebx, -12
100; X86-NEXT:    #APP
101; X86-EMPTY:
102; X86-NEXT:    movl -8(%ebp,%eax), %eax
103; X86-NEXT:    movl %eax, -8(%ebp,%eax)
104; X86-NEXT:    movl 262(%ebp,%ebx), %ebx
105; X86-NEXT:    movl %ebx, 820(%ebp,%ebx)
106; X86-NEXT:    movl %eax, 39(%ebp,%ebx)
107; X86-EMPTY:
108; X86-NEXT:    #NO_APP
109; X86-NEXT:    movl $2, -8(%ebp)
110; X86-NEXT:    addl $4, %esp
111; X86-NEXT:    popl %ebx
112; X86-NEXT:    popl %ebp
113; X86-NEXT:    .cfi_def_cfa %esp, 4
114; X86-NEXT:    retl
115;
116; X86PIC-LABEL: t2:
117; X86PIC:       # %bb.0: # %entry
118; X86PIC-NEXT:    pushl %ebp
119; X86PIC-NEXT:    .cfi_def_cfa_offset 8
120; X86PIC-NEXT:    .cfi_offset %ebp, -8
121; X86PIC-NEXT:    movl %esp, %ebp
122; X86PIC-NEXT:    .cfi_def_cfa_register %ebp
123; X86PIC-NEXT:    pushl %ebx
124; X86PIC-NEXT:    pushl %eax
125; X86PIC-NEXT:    .cfi_offset %ebx, -12
126; X86PIC-NEXT:    #APP
127; X86PIC-EMPTY:
128; X86PIC-NEXT:    movl -8(%ebp,%eax), %eax
129; X86PIC-NEXT:    movl %eax, -8(%ebp,%eax)
130; X86PIC-NEXT:    movl 262(%ebp,%ebx), %ebx
131; X86PIC-NEXT:    movl %ebx, 820(%ebp,%ebx)
132; X86PIC-NEXT:    movl %eax, 39(%ebp,%ebx)
133; X86PIC-EMPTY:
134; X86PIC-NEXT:    #NO_APP
135; X86PIC-NEXT:    movl $2, -8(%ebp)
136; X86PIC-NEXT:    addl $4, %esp
137; X86PIC-NEXT:    popl %ebx
138; X86PIC-NEXT:    popl %ebp
139; X86PIC-NEXT:    .cfi_def_cfa %esp, 4
140; X86PIC-NEXT:    retl
141entry:
142  %lVar = alloca i32, align 4
143  call void asm sideeffect inteldialect "mov eax, dword ptr $3[eax]\0A\09mov dword ptr $0[eax], eax\0A\09mov ebx, dword ptr $4[ebx + $$270]\0A\09mov dword ptr $1[ebx + $$828], ebx\0A\09mov $2[ebx + $$47], eax", "=*m,=*m,=*m,*m,*m,~{eax},~{ebx},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) %lVar, ptr elementtype(i32) %lVar, ptr elementtype(i32) %lVar, ptr elementtype(i32) %lVar, ptr elementtype(i32) %lVar)
144  store i32 2, ptr %lVar, align 4
145  ret void
146}
147
148attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
149attributes #1 = { nounwind }
150
151!llvm.module.flags = !{!0}
152
153!0 = !{i32 1, !"NumRegisterParameters", i32 0}
154