1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s 3 4define i32 @mask_negated_zext_bool1(i1 %x) { 5; CHECK-LABEL: mask_negated_zext_bool1: 6; CHECK: # %bb.0: 7; CHECK-NEXT: movl %edi, %eax 8; CHECK-NEXT: andl $1, %eax 9; CHECK-NEXT: retq 10 %ext = zext i1 %x to i32 11 %neg = sub i32 0, %ext 12 %and = and i32 %neg, 1 13 ret i32 %and 14} 15 16define i32 @mask_negated_zext_bool2(i1 zeroext %x) { 17; CHECK-LABEL: mask_negated_zext_bool2: 18; CHECK: # %bb.0: 19; CHECK-NEXT: movl %edi, %eax 20; CHECK-NEXT: retq 21 %ext = zext i1 %x to i32 22 %neg = sub i32 0, %ext 23 %and = and i32 %neg, 1 24 ret i32 %and 25} 26 27define <4 x i32> @mask_negated_zext_bool_vec(<4 x i1> %x) { 28; CHECK-LABEL: mask_negated_zext_bool_vec: 29; CHECK: # %bb.0: 30; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 31; CHECK-NEXT: retq 32 %ext = zext <4 x i1> %x to <4 x i32> 33 %neg = sub <4 x i32> zeroinitializer, %ext 34 %and = and <4 x i32> %neg, <i32 1, i32 1, i32 1, i32 1> 35 ret <4 x i32> %and 36} 37 38define i32 @mask_negated_sext_bool1(i1 %x) { 39; CHECK-LABEL: mask_negated_sext_bool1: 40; CHECK: # %bb.0: 41; CHECK-NEXT: movl %edi, %eax 42; CHECK-NEXT: andl $1, %eax 43; CHECK-NEXT: retq 44 %ext = sext i1 %x to i32 45 %neg = sub i32 0, %ext 46 %and = and i32 %neg, 1 47 ret i32 %and 48} 49 50define i32 @mask_negated_sext_bool2(i1 zeroext %x) { 51; CHECK-LABEL: mask_negated_sext_bool2: 52; CHECK: # %bb.0: 53; CHECK-NEXT: movl %edi, %eax 54; CHECK-NEXT: retq 55 %ext = sext i1 %x to i32 56 %neg = sub i32 0, %ext 57 %and = and i32 %neg, 1 58 ret i32 %and 59} 60 61define <4 x i32> @mask_negated_sext_bool_vec(<4 x i1> %x) { 62; CHECK-LABEL: mask_negated_sext_bool_vec: 63; CHECK: # %bb.0: 64; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 65; CHECK-NEXT: retq 66 %ext = sext <4 x i1> %x to <4 x i32> 67 %neg = sub <4 x i32> zeroinitializer, %ext 68 %and = and <4 x i32> %neg, <i32 1, i32 1, i32 1, i32 1> 69 ret <4 x i32> %and 70} 71 72