xref: /llvm-project/llvm/test/CodeGen/X86/legalize-vaarg.ll (revision 2f448bf509432c1a19ec46ab8cbc7353c03c6280)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2;RUN: llc < %s -mtriple=x86_64-- -mattr=avx | FileCheck %s
3
4define <32 x i32> @test_large_vec_vaarg(i32 %n, ...) {
5; CHECK-LABEL: test_large_vec_vaarg:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    movl -{{[0-9]+}}(%rsp), %ecx
8; CHECK-NEXT:    cmpl $24, %ecx
9; CHECK-NEXT:    jae .LBB0_2
10; CHECK-NEXT:  # %bb.1:
11; CHECK-NEXT:    movq {{[0-9]+}}(%rsp), %rax
12; CHECK-NEXT:    addq %rcx, %rax
13; CHECK-NEXT:    addl $8, %ecx
14; CHECK-NEXT:    movl %ecx, -{{[0-9]+}}(%rsp)
15; CHECK-NEXT:    jmp .LBB0_3
16; CHECK-NEXT:  .LBB0_2:
17; CHECK-NEXT:    movq (%rsp), %rax
18; CHECK-NEXT:    addq $31, %rax
19; CHECK-NEXT:    andq $-32, %rax
20; CHECK-NEXT:    leaq 32(%rax), %rcx
21; CHECK-NEXT:    movq %rcx, (%rsp)
22; CHECK-NEXT:  .LBB0_3:
23; CHECK-NEXT:    vmovaps (%rax), %ymm0
24; CHECK-NEXT:    movl -{{[0-9]+}}(%rsp), %ecx
25; CHECK-NEXT:    cmpl $24, %ecx
26; CHECK-NEXT:    jae .LBB0_5
27; CHECK-NEXT:  # %bb.4:
28; CHECK-NEXT:    movq {{[0-9]+}}(%rsp), %rax
29; CHECK-NEXT:    addq %rcx, %rax
30; CHECK-NEXT:    addl $8, %ecx
31; CHECK-NEXT:    movl %ecx, -{{[0-9]+}}(%rsp)
32; CHECK-NEXT:    jmp .LBB0_6
33; CHECK-NEXT:  .LBB0_5:
34; CHECK-NEXT:    movq (%rsp), %rax
35; CHECK-NEXT:    addq $31, %rax
36; CHECK-NEXT:    andq $-32, %rax
37; CHECK-NEXT:    leaq 32(%rax), %rcx
38; CHECK-NEXT:    movq %rcx, (%rsp)
39; CHECK-NEXT:  .LBB0_6:
40; CHECK-NEXT:    vmovaps (%rax), %ymm1
41; CHECK-NEXT:    movl -{{[0-9]+}}(%rsp), %ecx
42; CHECK-NEXT:    cmpl $24, %ecx
43; CHECK-NEXT:    jae .LBB0_8
44; CHECK-NEXT:  # %bb.7:
45; CHECK-NEXT:    movq {{[0-9]+}}(%rsp), %rax
46; CHECK-NEXT:    addq %rcx, %rax
47; CHECK-NEXT:    addl $8, %ecx
48; CHECK-NEXT:    movl %ecx, -{{[0-9]+}}(%rsp)
49; CHECK-NEXT:    jmp .LBB0_9
50; CHECK-NEXT:  .LBB0_8:
51; CHECK-NEXT:    movq (%rsp), %rax
52; CHECK-NEXT:    addq $31, %rax
53; CHECK-NEXT:    andq $-32, %rax
54; CHECK-NEXT:    leaq 32(%rax), %rcx
55; CHECK-NEXT:    movq %rcx, (%rsp)
56; CHECK-NEXT:  .LBB0_9:
57; CHECK-NEXT:    vmovaps (%rax), %ymm2
58; CHECK-NEXT:    movl -{{[0-9]+}}(%rsp), %ecx
59; CHECK-NEXT:    cmpl $24, %ecx
60; CHECK-NEXT:    jae .LBB0_11
61; CHECK-NEXT:  # %bb.10:
62; CHECK-NEXT:    movq {{[0-9]+}}(%rsp), %rax
63; CHECK-NEXT:    addq %rcx, %rax
64; CHECK-NEXT:    addl $8, %ecx
65; CHECK-NEXT:    movl %ecx, -{{[0-9]+}}(%rsp)
66; CHECK-NEXT:    vmovaps (%rax), %ymm3
67; CHECK-NEXT:    retq
68; CHECK-NEXT:  .LBB0_11:
69; CHECK-NEXT:    movq (%rsp), %rax
70; CHECK-NEXT:    addq $31, %rax
71; CHECK-NEXT:    andq $-32, %rax
72; CHECK-NEXT:    leaq 32(%rax), %rcx
73; CHECK-NEXT:    movq %rcx, (%rsp)
74; CHECK-NEXT:    vmovaps (%rax), %ymm3
75; CHECK-NEXT:    retq
76  %args = alloca ptr, align 4
77  %x = va_arg ptr %args, <32 x i32>
78  ret <32 x i32> %x
79}
80