xref: /llvm-project/llvm/test/CodeGen/X86/lea-2.ll (revision 8bd16789ff0af00270936c4536dd18b48e4d3897)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-linux          | FileCheck %s --check-prefix=X86
3; RUN: llc < %s -mtriple=x86_64-linux        | FileCheck %s --check-prefix=X64
4; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s --check-prefix=X64
5; RUN: llc < %s -mtriple=x86_64-nacl         | FileCheck %s --check-prefix=X64
6
7; The computation of %t4 should match a single lea, without using actual add instructions.
8
9define i32 @test1(i32 %A, i32 %B) {
10; X86-LABEL: test1:
11; X86:       # %bb.0:
12; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
13; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
14; X86-NEXT:    leal -5(%ecx,%eax,4), %eax
15; X86-NEXT:    retl
16;
17; X64-LABEL: test1:
18; X64:       # %bb.0:
19; X64-NEXT:    # kill: def $esi killed $esi def $rsi
20; X64-NEXT:    # kill: def $edi killed $edi def $rdi
21; X64-NEXT:    leal -5(%rsi,%rdi,4), %eax
22; X64-NEXT:    retq
23  %t1 = shl i32 %A, 2
24  %t3 = add i32 %B, -5
25  %t4 = add i32 %t3, %t1
26  ret i32 %t4
27}
28
29; The addlike OR instruction should fold into the LEA.
30
31define i64 @test2(i32 %a0, i64 %a1) {
32; X86-LABEL: test2:
33; X86:       # %bb.0:
34; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
35; X86-NEXT:    movl %edx, %eax
36; X86-NEXT:    andl $2147483640, %eax # imm = 0x7FFFFFF8
37; X86-NEXT:    shrl $31, %edx
38; X86-NEXT:    leal 4(%eax,%eax), %eax
39; X86-NEXT:    addl {{[0-9]+}}(%esp), %eax
40; X86-NEXT:    adcl {{[0-9]+}}(%esp), %edx
41; X86-NEXT:    retl
42;
43; X64-LABEL: test2:
44; X64:       # %bb.0:
45; X64-NEXT:    # kill: def $edi killed $edi def $rdi
46; X64-NEXT:    andl $-8, %edi
47; X64-NEXT:    leaq 4(%rsi,%rdi,2), %rax
48; X64-NEXT:    retq
49  %x1 = and i32 %a0, -8
50  %x2 = or i32 %x1, 2
51  %x3 = zext i32 %x2 to i64
52  %x4 = shl i64 %x3, 1
53  %x5 = add i64 %a1, %x4
54  ret i64 %x5
55}
56